公开(公告)号：EP0570595B1

公开(公告)日：1998-03-11

申请号：EP92924886.2

申请日：1992-12-07

申请人： DENSO CORPORATION

发明人： TOKURA, Norihito Nippondenso Co., Ltd. ,  OKABE, Naoto Nippondenso Co., Ltd. 1-1, Showa-cho

IPC分类号： H01L29/772 ,  H01L29/72

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

摘要： Arsenic is diffused in advance into the uppermost surface of an n type epitaxial layer (2) to form a gate oxide film (3) and gate electrodes (4). Then, a p-type base region (8) and an n type source layer (7) are formed by a DSA technique and double diffusion in a self-alignment manner with the gate electrode (4). Hence, in the uppermost surface, the junction depth of the p-type base regions (8) in the lateral direction is compensated, and the channel length of channels (9) is shortened substantially. Also, when a threshold voltage is designed in the same manner as conventionally designed, it is possible to make the impurity density of the p-type base region (8) higher by the amount of the impurity density of the arsenic in the uppermost surface. Thus, the resistance value of p-type pinch layer (14) formed directly under the n source layer (7) of the p-type base region (8) can be reduced by the amount.

公开(公告)号：EP0550770B1

公开(公告)日：1997-11-12

申请号：EP92916224.6

申请日：1992-07-22

申请人： DENSO CORPORATION

发明人： TOKURA, Norihito Nippondenso Co., Ltd. ,  TAKAHASHI, Shigeki Nippondenso Co., Ltd.

IPC分类号： H01L29/772 ,  H01L29/41

CPC分类号： H01L29/7813 ,  H01L21/28167 ,  H01L21/28211 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

摘要： A vertical power MOSFET which has a markedly decreased on-resistance per unit area. A groove having a gate structure is substantially formed by the LOCOS method prior to forming the p-type base layer and the n -type source layer. Then, the p-type base layer (16) and the n -type source layer (4) are formed by double diffusion being self-aligned with the LOCOS oxide film (65) and, at the same time, a channel (5) is set in the sidewall (51) of the LOCOS oxide film. Then, the LOCOS oxide film is removed to form a U-groove thereby to constitute the gate structure. That is, the channel is set by double diffusion which is self-aligned to the LOCOS oxide film, i.e., the channels are correctly set symmetrically in the sidewalls on both sides of the groove. Therefore, the position of the U-groove is not deviated with respect to the end of the base layer, and the length of the bottom surface of the U-groove can be minimized. This makes it possible to greatly decrease the size of the unit cell and to greatly decrease the on-resistance per unit area.