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    Manufacturing method of a field effect semiconductor device
    2.
    发明授权
    Manufacturing method of a field effect semiconductor device 失效
    的场效应半导体装置的制造方法

    公开(公告)号：EP0675530B1

    公开(公告)日：2000-09-06

    申请号：EP95104752.1

    申请日：1995-03-30

    申请人： DENSO CORPORATION

    发明人： Takahashi, Shigeki ,  Kataoka, Mitsuhiro ,  Yamamoto, Tsuyoshi

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/316

    CPC分类号： H01L29/7813 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  Y10S148/126

    摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part (64) is thermally oxidized by using a silicon nitride film (63) as a mask. A LOCOS oxide film (65) is formed by this thermal oxidation, and concurrently a U-groove (50) is formed on the surface of an n -type epitaxial layer (2) eroded by the LOCOS oxide film (65), and the shape of the U-groove (50) is fixed. A curve part (709) formed during a chemical dry etching process remains as a curve part (710) on the side surface of the U-groove (50). Then, an n -type source layer (4) is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 mu m, and a channel (5) is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part (710) which is formed during the above etching and remains on the side surface of the U-groove (50) after the above selective thermal oxidation.

    LATERAL FIELD EFFECT TRANSISTOR HAVING REDUCED DRAIN-TO-SOURCE ON-RESISTANCE
    3.
    发明公开
    LATERAL FIELD EFFECT TRANSISTOR HAVING REDUCED DRAIN-TO-SOURCE ON-RESISTANCE 失效
    LA ER AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND

    公开(公告)号：EP0826244A4

    公开(公告)日：1998-05-13

    申请号：EP96912472

    申请日：1996-04-04

    申请人： SILICONIX INC

    发明人： HSHIEH FWU-IUAN ,  CHANG MIKE F ,  VAN DER LINDE JAN ,  HO YUEH-SE

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66719 ,  H01L29/7802 ,  Y10S148/126

    摘要： A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the substrate upon which the transistor structure is formed. When the transistor is turned on, the channel region inverts thereby forming a conductive path from a source region, laterally through the inverted channel region, substantially vertically through a sinker region to the underlying substrate, through the substrate, and to the drain electrode.

    摘要翻译： 功率场效应晶体管具有不由双扩散形成的横向延伸的沟道区。 沟道区可以在外延硅中形成，其在生长后不被掺杂。 晶体管的漏电极设置在其上形成晶体管结构的衬底的底表面上。 当晶体管导通时，沟道区域反转，从而从源极区域侧向穿过反向沟道区域，基本垂直地穿过沉降片区域到底层衬底，通过衬底和漏电极形成导电路径。

    METHOD OF PRODUCING VERTICAL MOSFETS
    5.
    发明授权
    METHOD OF PRODUCING VERTICAL MOSFETS 失效
    生产工艺的MOSFET垂直

    公开(公告)号：EP0550770B1

    公开(公告)日：1997-11-12

    申请号：EP92916224.6

    申请日：1992-07-22

    申请人： DENSO CORPORATION

    发明人： TOKURA, Norihito Nippondenso Co., Ltd. ,  TAKAHASHI, Shigeki Nippondenso Co., Ltd.

    IPC分类号： H01L29/772 ,  H01L29/41

    CPC分类号： H01L29/7813 ,  H01L21/28167 ,  H01L21/28211 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

    摘要： A vertical power MOSFET which has a markedly decreased on-resistance per unit area. A groove having a gate structure is substantially formed by the LOCOS method prior to forming the p-type base layer and the n -type source layer. Then, the p-type base layer (16) and the n -type source layer (4) are formed by double diffusion being self-aligned with the LOCOS oxide film (65) and, at the same time, a channel (5) is set in the sidewall (51) of the LOCOS oxide film. Then, the LOCOS oxide film is removed to form a U-groove thereby to constitute the gate structure. That is, the channel is set by double diffusion which is self-aligned to the LOCOS oxide film, i.e., the channels are correctly set symmetrically in the sidewalls on both sides of the groove. Therefore, the position of the U-groove is not deviated with respect to the end of the base layer, and the length of the bottom surface of the U-groove can be minimized. This makes it possible to greatly decrease the size of the unit cell and to greatly decrease the on-resistance per unit area.

    Extended drain resurf lateral DMOS devices
    8.
    发明公开
    Extended drain resurf lateral DMOS devices 失效
    废水 - DMOS-Bauelemente mit erweitertem排水。

    公开(公告)号：EP0676799A2

    公开(公告)日：1995-10-11

    申请号：EP95105403.0

    申请日：1995-04-10

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Mei, Chia-Cu P. ,  Malhi, Satwinder

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S148/126

    摘要： A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.

    摘要翻译： 高电压PMOS晶体管7通过调整轻掺杂漂移区域边缘48中的杂质浓度来改善导通电阻，以补偿在厚场氧化物43的生长阶段期间发生的杂质偏析。在制造高电压PMOS器件7期间， 通过杂质偏析形成场氧化物43形成的浅垂直结230.注入HV漂移区域p型槽边缘调节件220并进行退火形成横向接合部250，并将浅结230隔离在场氧化物43下。由此，导通电阻 高电压PMOS晶体管7最小化。

    A bidirectional blocking lateral mosfet with improved on-resistance
    9.
    发明公开
    A bidirectional blocking lateral mosfet with improved on-resistance 失效
    具有改进的导通电阻的双向阻断横向MOSFET

    公开(公告)号：EP0656662A3

    公开(公告)日：1995-08-02

    申请号：EP94308842.7

    申请日：1994-11-30

    申请人： SILICONIX INCORPORATED

    发明人： William, Richard K. ,  Jew, Kevin ,  Chen, Jun Wei

    IPC分类号： H01L29/78 ,  H01L29/10

    CPC分类号： H01L29/78 ,  H01L29/1087 ,  Y10S148/126

    摘要： A bidirectional current blocking lateral MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the oxide layer and a channel of the body region separating the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.

    摘要翻译： 包括源极和漏极的双向电流阻断横向MOSFET不与衬底短路，并且施加到源极和漏极的电压都高于维持本体的电压（对于N沟道MOSFET） 或低于身体维持的电压（对于P沟道MOSFET）。 MOSFET的导通电阻通过减小epi区域的电导并且在氧化物层与分离源极和漏极区域的主体区域的沟道之间的衬底表面上设置薄的阈值调节层而得以改善。 在衬底表面上设置可选的第二穿通防止注入。

    Process for forming a buried drain or collector region in monolithic semiconductor devices
    10.
    发明公开
    Process for forming a buried drain or collector region in monolithic semiconductor devices 失效
    用于在单片半导体器件中形成掩埋漏极或集电极区的工艺

    公开(公告)号：EP0453026A3

    公开(公告)日：1995-02-15

    申请号：EP91200853.9

    申请日：1991-04-11

    申请人： CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    发明人： Zambrano, Raffaele

    IPC分类号： H01L21/74 ,  H01L29/06

    CPC分类号： H01L29/7802 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712 ,  Y10S148/126 ,  Y10S438/98

    摘要： The invention relates to a process for forming a buried drain (3) or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions (3) of high dopant concentration defined after growth of a first epitaxial layer (2).

    摘要翻译： 本发明涉及一种用于在单片半导体器件中形成掩埋漏极（3）或集电极区域的工艺，所述单片半导体器件包括集成控制电路和集成在同一芯片中的具有垂直电流的一个或多个功率晶体管。 与已知结构相比，通过提供一个或多个在第一外延层生长之后限定的高掺杂浓度的区域（3），该工艺允许优化功率级和工作电压的载流容量和串联漏极电阻（ 2）。