公开(公告)号：EP0748537A4

公开(公告)日：1998-06-17

申请号：EP95913556

申请日：1995-03-02

申请人： ECHELON CORP

发明人： SUTTELRIN PHILIP H ,  DOWNEY WALTER J

IPC分类号： H03M3/02

CPC分类号： H03M3/39 ,  H03M3/332 ,  H03M3/43 ,  H03M3/456

摘要： A sigma-delta A/D converter (301) having a digital logic gate core. The converter is comprised of a loop filter (304) for shaping the converter's quantization noise spectrum. The loop filter is comprised of an unbuffered CMOS logic gate inverter (602) which can be implemented by a gate array. A quantizer (305) is coupled to the loop filter. A logic gate buffer (501) is configured as a one-bit comparator, which is used to perform the quantization. This logic gate buffer can be one of the gates of a gate array. A sample (306) is coupled to the quantizer for sampling the quantized signal. This sampler can also be implemented by digital circuitry of a gate array. The signal from the sampler is fed into a decimator (302). The decimator outputs a digital signal representative of the amplitude of the analog signal.

公开(公告)号：EP0754379A4

公开(公告)日：2000-12-13

申请号：EP95916175

申请日：1995-03-30

申请人： ECHELON CORP

发明人： HURLBUT AMY O ,  SUTTERLIN PHILIP H ,  DOWNEY WALTER J

IPC分类号： H03M13/09 ,  H03M13/21 ,  H03M13/25 ,  H03M13/29 ,  H03M13/45 ,  H04L1/00 ,  H04L25/49 ,  H04L27/18 ,  H04L27/00

CPC分类号： H04L27/18 ,  H03M13/096 ,  H03M13/21 ,  H03M13/25 ,  H04L1/0061 ,  H04L25/4906

摘要： In a system for encoding/decoding phase modulated data, each data word (520) includes 8 data bits, a parity bit, and ends with two coding bits. A transmitted BPSK signal is demodulated into a recovered signal that is decoded using a rotating reference frame that tracks the signal phase. The signal is compared against the reference frame and the signal phase characteristics are recorded for determining a bit position of a large phase shift most likely to cause a data inversion. A single bit error detected (2310) with the parity bit is corrected (2520) by inverting the bit having the smallest measured amplitude in the recovered signal of the data word. An inversion detected (2550) by the two coding bits is corrected (2720, 2725) by inverting each successive bit starting from the position with the large phase shift. Parity is rechecked (2730), and any single bit error is corrected (2735).

公开(公告)号：EP1839391A4

公开(公告)日：2010-02-24

申请号：EP05791793

申请日：2005-08-24

申请人： ECHELON CORP

发明人： DOWNEY WALTER J ,  WILSON JACQUES H II

IPC分类号： H03K17/13 ,  G05B24/02 ,  H05B39/04

CPC分类号： H05B39/00 ,  H02M5/257 ,  H02M2001/0006

公开(公告)号：EP0754376A4

公开(公告)日：1999-04-07

申请号：EP95915554

申请日：1995-04-05

申请人： ECHELON CORP

发明人： SUTTERLIN PHILIP H ,  DOWNEY WALTER J ,  CHUI BENJAMIN W ,  STEWART J MARCUS ,  HURLBUT AMY O

IPC分类号： H03G3/34 ,  H04B3/54 ,  H04B3/56 ,  H04B1/10

CPC分类号： H04B3/542 ,  H03G3/345 ,  H04B3/56 ,  H04B2203/5416 ,  H04B2203/545 ,  H04B2203/547

摘要： An apparatus for snubbing or blanking digital signals representing a band of signals that includes an encoded carrier signal transmitted over a power line. An average signal level (SNAVG) is compared with the instantaneous signal level to develop a blanking circuit control signal (SNGT). Additionally, snubbing occurs in the circuit (24) which determines the average signal level, to prevent noise from building up the average signal level. A hold-off signal (SNHO) is used in this circuit to prevent the average signal level (SNAVG) from being latched permanently low. A unique infinite impulse filter (17) subtracts out the D.C. offset, thereby improving the dynamic range of the blanking. Additionally, the average signal level (SNAVG) is used by AGC logic (25) to control the gain at the front end (14) of the apparatus. The state and switching of the AGC is controlled to minimize errors.