公开(公告)号：EP1776762B1

公开(公告)日：2012-02-01

申请号：EP05775248.7

申请日：2005-07-25

申请人： Easic Corporation ,  Kapel, Alon ,  Grigore, George Catalin

发明人： OR-BACH, Zvi ,  AVRAM, Petrica ,  IACOBUT, Romeo ,  APOSTOL, Adrian ,  WURMAN, Ze'ev ,  LEVENTHAL, Adam ,  ZEMAN, Richard ,  KAPEL, Alon ,  GRIGORE, George, Catalin

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.