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公开(公告)号：EP1776762A2
公开(公告)日：2007-04-25
申请号：EP05775248.7
申请日：2005-07-25
发明人： OR-BACH, Zvi , AVRAM, Petrica , IACOBUT, Romeo , APOSTOL, Adrian , WURMAN, Ze'ev , LEVENTHAL, Adam , ZEMAN, Richard
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
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公开(公告)号：EP1776762B1
公开(公告)日：2012-02-01
申请号：EP05775248.7
申请日：2005-07-25
发明人： OR-BACH, Zvi , AVRAM, Petrica , IACOBUT, Romeo , APOSTOL, Adrian , WURMAN, Ze'ev , LEVENTHAL, Adam , ZEMAN, Richard , KAPEL, Alon , GRIGORE, George, Catalin
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
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公开(公告)号：EP1161797A1
公开(公告)日：2001-12-12
申请号：EP00909601.7
申请日：2000-03-10
申请人： Easic Corporation
发明人： OR-BACH, Zvi , WURMAN, Ze'ev , ZEMAN, Richard , COOKE, Laurance
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17764 , H03K19/1778 , H03K19/17796
摘要： This invention discloses a personalizable and programmable integrated circuit device including at least first and second programmable logic cells (46), and at least two electrical conductive paths (28) interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
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公开(公告)号：EP1161797B1
公开(公告)日：2004-12-22
申请号：EP00909601.7
申请日：2000-03-10
申请人： Easic Corporation
发明人： OR-BACH, Zvi , WURMAN, Ze'ev , ZEMAN, Richard , COOKE, Laurance
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17764 , H03K19/1778 , H03K19/17796
摘要： This invention discloses a personalizable and programmable integrated circuit device including at least first and second programmable logic cells (46), and at least two electrical conductive paths (28) interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
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