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公开(公告)号：EP2073472A1
公开(公告)日：2009-06-24
申请号：EP08150379.9
申请日：2008-01-17
申请人： Eqcologic NV
IPC分类号： H04L25/06
CPC分类号： H04L25/06
摘要： The present invention provides a device for restoring a DC component in a differential digital data stream. The device comprises a first and second peak detector for detecting peaks in the differential digital data stream, a memory element for storing an average of the first and second detected peak signals during rich data patterns, an error signal selector for error signal selection, and a regulator for negative feedback of a selected error signal. The selected error signal is either the average of the detected peak signals stored on the memory element minus the signal at the output of the first peak detector, or the signal at the output of the second peak detector minus the average of the detected peak signals stored on the memory element.
摘要翻译： 本发明提供一种用于恢复差分数字数据流中的DC分量的装置。 该装置包括用于检测差分数字数据流中的峰值的第一和第二峰值检测器，用于在富数据模式期间存储第一和第二检测到的峰值信号的平均值的存储元件，用于误差信号选择的误差信号选择器，以及 调节器用于所选误差信号的负反馈。 选择的误差信号是存储在存储器元件上的检测到的峰值信号的平均值减去第一峰值检测器的输出处的信号，或第二峰值检测器的输出处的信号减去存储的检测到的峰值信号的平均值 在内存元素上。
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2.发明授权
公开(公告)号：EP2506514B1
公开(公告)日：2014-07-23
申请号：EP12174398.3
申请日：2009-04-30
申请人： EqcoLogic NV
发明人： Devuyst, Bram , Kuijk, Maarten
CPC分类号： H04L5/1407 , H04B3/548 , H04L5/14 , H04L5/1423 , H04L5/1461 , H04L12/5602 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/0298 , H04L25/03878 , H04L47/10 , H04L47/22 , H04L47/30 , H04L47/35
摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises: an input port (204) for receiving a low bitrate input data signal (101), an output port (202) for delivering a high bitrate output data signal (102), a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105), a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202). The transceiver circuit (212) may be incorporated in a transceiver (200).
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3.发明公开
公开(公告)号：EP2506514A1
公开(公告)日：2012-10-03
申请号：EP12174398.3
申请日：2009-04-30
申请人： EqcoLogic NV
发明人： Devuyst, Bram , Kuijk, Maarten
CPC分类号： H04L5/1407 , H04B3/548 , H04L5/14 , H04L5/1423 , H04L5/1461 , H04L12/5602 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/0298 , H04L25/03878 , H04L47/10 , H04L47/22 , H04L47/30 , H04L47/35
摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises:
an input port (204) for receiving a low bitrate input data signal (101),
an output port (202) for delivering a high bitrate output data signal (102),
a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105),
a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and
a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202).
The transceiver circuit (212) may be incorporated in a transceiver (200).
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