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    TERMINATION TOPOLOGY OF MEMORY SYSTEM AND ASSOCIATED MEMORY MODULE AND CONTROL METHOD
    4.
    发明公开
    TERMINATION TOPOLOGY OF MEMORY SYSTEM AND ASSOCIATED MEMORY MODULE AND CONTROL METHOD 审中-公开
    存储器系统的终止拓扑及相关存储器模块和控制方法

    公开(公告)号：EP3208806A1

    公开(公告)日：2017-08-23

    申请号：EP17156430.5

    申请日：2017-02-16

    申请人： MediaTek Inc.

    发明人： CHEN, Shang-Pin ,  HSIEH, Bo-Wei

    IPC分类号： G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C5/04 ,  G06F13/40 ,  H03K19/00 ,  H04L25/02

    CPC分类号： G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

    摘要： A memory system (100) includes a memory controller (110) and a memory module (120). The memory controller (110) is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module (120) includes a first termination resistor (ODT1), a second termination resistor (ODT2) and a switch module (222), where a first node of the first termination resistor (ODT1) is to receive the clock signal, a first node of the second termination resistor (ODT2) is to receive the inverted clock signal, and the switch module (222) is arranged for selectively connecting or disconnecting a second node of the second termination resistor (ODT2) to a second node of the first termination resistor (ODT1).

    摘要翻译： 存储器系统（100）包括存储器控制器（110）和存储器模块（120）。 存储器控制器（110）被布置为选择性地产生至少时钟信号和反相时钟信号。 存储器模块120包括第一终端电阻ODT1，第二终端电阻ODT2和开关模块222，第一终端电阻ODT1的第一节点接收时钟信号， 第二端接电阻器（ODT2）的第一节点将接收反相时钟信号，并且开关模块（222）被布置为选择性地将第二端接电阻器（ODT2）的第二节点连接到或断开到第一节点 终端电阻（ODT1）。

    Interface circuit
    9.
    发明公开
    Interface circuit 有权
    Schnittstellenschaltung

    公开(公告)号：EP2933923A1

    公开(公告)日：2015-10-21

    申请号：EP15150905.6

    申请日：2015-01-13

    申请人： Samsung Display Co., Ltd.

    发明人： Kim, Do-Ik

    IPC分类号： H03K19/013 ,  H03K19/017 ,  H04L25/02

    CPC分类号： H03K3/013 ,  G05F3/267 ,  H03K3/012 ,  H03K19/0136 ,  H03K19/01721 ,  H04L25/0298

    摘要： An interface circuit comprises a first integrated circuit (200) to transmit or receive data, a second integrated circuit (300) connected to the first integrated circuit by a transmission line (TL) to transmit or receive data, and a constant current generating circuit (100) connected to the transmission line so as to output a current of a constant magnitude (I2) to the transmission line. The constant current generating circuit (100) adjusts the amount of current (I2) outputted to the transmission line by sensing a voltage level (N1) of the transmission line.

    摘要翻译： 接口电路包括用于发送或接收数据的第一集成电路（200），通过传输线（TL）连接到第一集成电路以发送或接收数据的第二集成电路（300）和恒定电流产生电路 100）连接到传输线，以将恒定大小（I2）的电流输出到传输线。 恒流产生电路（100）通过感测传输线的电压电平（N1）来调节输出到传输线的电流量（I2）。

    Integrated circuit for emulating a resistor
    10.
    发明公开
    Integrated circuit for emulating a resistor 有权
    集成电路以模拟电阻

    公开(公告)号：EP2456152A3

    公开(公告)日：2015-04-15

    申请号：EP11188022.5

    申请日：2011-11-07

    申请人： NXP B.V.

    发明人： Den Besten, Gerrit

    IPC分类号： H04L25/02

    CPC分类号： H04L25/0298

    摘要： An integrated circuit for emulating a resistor is based on the output resistance of a non-linear circuit element, such as a transistor. In the case of a transistor, it is biased into operation in its linear region, and a voltage dependent on the ac source-drain voltage is coupled to the gate voltage, thereby to improve linearity of the drain-source resistance with respect to the drain-source voltage. This modification to the gate voltage can be used to alter the transfer function such that the drain-source resistance is no longer dependent on the drain-source voltage.