公开(公告)号：EP0136205B1

公开(公告)日：1988-06-01

申请号：EP84401608.9

申请日：1984-08-01

申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

发明人： Schinabeck, John ,  Murdock, James R.

IPC分类号： G01R31/28

CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

公开(公告)号：EP0136205A1

公开(公告)日：1985-04-03

申请号：EP84401608.9

申请日：1984-08-01

申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

发明人： Schinabeck, John ,  Murdock, James R.

IPC分类号： G01R31/28

CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

摘要： A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Progammable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing. Other features are also disclosed.

摘要翻译： 的测试信号施加和监测电路耦合到电子装置的销的多个被测试以迫使测试激励下测试信号到该装置的输入引脚。 当所述设备被测试的响应信号受到监控。 施加和监测电路中的每个测试信号包括节点被耦合到所述被测装置的销，一个数字编程源用于通过第一开关供给的测试信号连接到所述节点，和一个比较电路由连接到节点 用于相对于编程的参考电平指示响应信号的相对幅度第二开关。 的数字编程的源包括用于功能测试期间提供门控电压 - 电流交叉强制功能当被测试的设备被连接，以最小化干扰，并保护超出公差装置。 Progammable电压和电流值确定合适的窗口，以确保一个nonambiguous合格/去测试期间产生的。 其他功能使游离缺失盘。