BOOT LOADING SYSTEM IN A MULTI-PROCESSOR SYSTEM.
    4.
    发明公开
    BOOT LOADING SYSTEM IN A MULTI-PROCESSOR SYSTEM. 失效
    URLADUNGSSYSTEM在多处理器系统。

    公开(公告)号:EP0270680A4

    公开(公告)日:1988-09-28

    申请号:EP87903404

    申请日:1987-05-16

    申请人: FANUC LTD

    发明人: YONEKURA MIKIO

    CPC分类号: G06F15/177 G06F9/4405

    摘要: A boot loading system which down-loads a program onto a plurality of volatile memories from an auxiliary memory device when the power source of the multi-processor system is switched on. A loader ROM (42) is shared, and a program is down-loaded onto volatile memories (12, 22, 32) of respective processors (11, 21, 31) by a program of the loader ROM (42) when the power source is switched on. This enables the loader ROM to be reduced and the loading control to be simplified.

    CONTROLLER WITH STATUS DISPLAY UNIT.
    5.
    发明公开
    CONTROLLER WITH STATUS DISPLAY UNIT. 失效
    切换到计量单元。

    公开(公告)号:EP0126163A4

    公开(公告)日:1987-02-03

    申请号:EP83903580

    申请日:1983-11-21

    申请人: FANUC LTD

    IPC分类号: G05B23/02 G05B19/05 G01D7/00

    CPC分类号: G05B19/058 G05B2219/14089

    摘要: A controller, such as a numerical controller, displays the changewith time of input/output statuses or an internal status by a timing chart, to facilitate analysis of the cause of interference concerning signal timing. The controller has a status display unit (22) which includes: a keyboard (25) for inputting desired display data, display data input times, and display data input-inhibit conditions; a timer (26) which generates a clock signal at predetermined timing; a memory (27) which inputs desired display data during an interval of a desired input time in accordance with the conditions set through the keyboard; a display (28) which displays the data input to the memory when the input-inhibit conditions are satisfied; and a processor (29) which controls the memory and the display in synchronism with the clock signal.