公开(公告)号：EP0540105A3

公开(公告)日：1993-09-08

申请号：EP92203270.1

申请日：1992-10-23

申请人： FLUKE CORPORATION

发明人： Noordeloos, Jacob Hendrik ,  Rensink, Anton Hendrik ,  Sankaranarayanan, Lakshmi Narayanan

IPC分类号： G11C27/04

CPC分类号： G11C27/04

摘要： A sampling device (12) for a digital measuring instrument (1) is provided, which device (12) operates on the basis of time conversion. Compared with known sampling devices with time conversion based on CCD technology, the sampling device according to the invention comprises a retiming switch (d1) for retiming analog signals followed by a charge demultiplexing circuit (dmx) which operates in the charge domain. The charge demultiplexing circuit (dmx) is followed by a CCD array (pch0 to pch7) for storage of charge packages of the signal to be converted. The CCD structure, which is filled with charge packages at high speed, is read out at a much lower speed. The CCD structure according to the invention is optimally utilized through a suitable choice of control signals and is easy to control. Furthermore, less high requirements are set for the CCD drivers ad the peripheral clock system.

摘要翻译： 提供了一种用于数字测量仪器（1）的采样设备（12），该设备（12）基于时间转换操作。 与基于CCD技术的具有时间转换的已知采样装置相比，根据本发明的采样装置包括重新定时开关（d1），用于重新定时模拟信号，随后是在电荷域中操作的电荷解复用电路（dmx）。 电荷解复用电路（dmx）之后是用于存储要转换的信号的电荷封装的CCD阵列（pch0至pch7）。 以高速度充满电荷包装的CCD结构以低得多的速度读出。 根据本发明的CCD结构通过合适的控制信号选择被最佳地利用并且易于控制。 此外，CCD驱动器和外设时钟系统的要求较低。

公开(公告)号：EP0540105A2

公开(公告)日：1993-05-05

申请号：EP92203270.1

申请日：1992-10-23

申请人： FLUKE CORPORATION

发明人： Noordeloos, Jacob Hendrik ,  Rensink, Anton Hendrik ,  Sankaranarayanan, Lakshmi Narayanan

IPC分类号： G11C27/04

CPC分类号： G11C27/04

摘要： A sampling device (12) for a digital measuring instrument (1) is provided, which device (12) operates on the basis of time conversion. Compared with known sampling devices with time conversion based on CCD technology, the sampling device according to the invention comprises a retiming switch (d1) for retiming analog signals followed by a charge demultiplexing circuit (dmx) which operates in the charge domain. The charge demultiplexing circuit (dmx) is followed by a CCD array (pch0 to pch7) for storage of charge packages of the signal to be converted. The CCD structure, which is filled with charge packages at high speed, is read out at a much lower speed. The CCD structure according to the invention is optimally utilized through a suitable choice of control signals and is easy to control. Furthermore, less high requirements are set for the CCD drivers ad the peripheral clock system.

摘要翻译： 的取样装置（12），用于数字测量仪器（1）被提供，该装置（12）操作时间转换的基础上。 与基于CCD技术时间转换的已知采样装置相比，取样装置gemäß到本发明包括用于再定时随后分批多路分解电路（DMX）中的电荷域其操作的模拟信号重新定时开关（D1）。 将批料多路分解电路（DMX）由CCD阵列（pch0到pch7）为的信号电荷的包存储要转换其次。 填充有在高速充电包CCD结构，所有，是在低得多的速度被读出。 的CCD结构雅丁的发明是通过控制信号的适当选择可利用的OPTI马利和易于控制。 此外更多，更少高的要求的驱动CCD广告外设时钟系统设置。