公开(公告)号：EP2703944A2

公开(公告)日：2014-03-05

申请号：EP13181734.8

申请日：2013-08-26

申请人： FUJITSU LIMITED

发明人： Koinuma, Hideyuki ,  Fukumura, Hiromi ,  Hara, Michiharu ,  Kageyama, Hironobu ,  Yoshida, Toshio

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/324 ,  G06F1/28 ,  G06F1/3206 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D50/20

摘要： When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.

摘要翻译： 当电流传感器22的检测结果表示过电流的发生时，PSU的比较器23向SP 1发送指示该事实的当前报告。接收到本报告，SP1的FPGA12接通强制 低功率信号。 CPU3的强制省电控制电路32直接输入强制低功率模式信号，接通信号，并且控制配置为在CPU 3中发出指令的指令发布控制单元，以便 立即降低指令发布控制单元发出指令的频率。 在DVFS控制电路35降低从DDC 4输出的电力电压和从PLL电路输出的时钟频率之后，该控制被取消。

公开(公告)号：EP4350499A1

公开(公告)日：2024-04-10

申请号：EP23183280.9

申请日：2023-07-04

申请人： Fujitsu Limited

发明人： Ogihara, Kazutaka ,  Shiraishi, Takashi ,  Otsuka, Masato ,  Nishio, Naoya ,  Fukumura, Hiromi ,  Kondo, Reiko

IPC分类号： G06F3/06

摘要： A method includes calculating a plurality of first index values indicating access loads from one or more first virtual storage devices accessing a first physical storage device of a plurality of physical storage devices, to the first physical storage device, in a case where access loads from the one or more first virtual storage devices to a plurality of second physical storage devices including the first physical storage device are equalized across the second physical storage devices, the plurality of second physical storage devices being associated with the one or more first virtual storage devices; and outputting a plurality of second index values indicating access loads from a plurality of virtual machines to the first physical storage device, the second index values being obtained by summing the calculated first index values for each virtual machine associated with each of the one or more first virtual storage devices.

公开(公告)号：EP2498163A3

公开(公告)日：2018-03-14

申请号：EP12158299.3

申请日：2012-03-06

申请人： Fujitsu Limited

发明人： Okano, Kenji ,  Gotsubo, Kenji ,  Yamada, Tadashi ,  Fukumura, Hiromi

IPC分类号： G06F1/14

CPC分类号： G06F1/14

摘要： In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.

摘要翻译： 在信息处理设备中，控制单元包括用于提供一天中的时间的第一时钟装置。 物理域包括第二时钟设备，并且实现用作虚拟信息处理设备的逻辑域。 控制单元控制第一时钟设备的时间与第二时钟设备的时间之间的第一时间差。 物理域控制第二个时钟设备的时间与逻辑域的时间之间的第二个时间差。 在该信息处理设备中，基于第一和第二时间差异来控制逻辑域上的时间。

公开(公告)号：EP2704016A2

公开(公告)日：2014-03-05

申请号：EP13180054.2

申请日：2013-08-12

申请人： FUJITSU LIMITED

发明人： Fukumura, Hiromi ,  Suga, Katsuya

IPC分类号： G06F13/16

CPC分类号： G06F12/0246 ,  G06F1/3275 ,  G06F11/106 ,  G06F13/1657 ,  G06F13/1668 ,  Y02D10/13 ,  Y02D10/14

摘要： A disclosed information processing apparatus includes: one or plural memories, each of which includes a self-refresh function; and a memory control unit that stops a patrol that includes reading and error correction with respect to a memory among the one or plural memories, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories.

摘要翻译： 公开的信息处理设备包括：一个或多个存储器，每个存储器包括自刷新功能; 以及存储器控制单元，当开始对所述一个或多个存储器的自刷新时，停止包括对所述一个或多个存储器中的存储器的读取和纠错的巡检，并且在停止所述一个或多个存储器的重新开始时， 刷新一个或多个记忆。

公开(公告)号：EP2703944A3

公开(公告)日：2016-07-27

申请号：EP13181734.8

申请日：2013-08-26

申请人： FUJITSU LIMITED

发明人： Koinuma, Hideyuki ,  Fukumura, Hiromi ,  Hara, Michiharu ,  Kageyama, Hironobu ,  Yoshida, Toshio

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/324 ,  G06F1/28 ,  G06F1/3206 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D50/20

摘要： When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.

公开(公告)号：EP2704016A3

公开(公告)日：2014-10-29

申请号：EP13180054.2

申请日：2013-08-12

申请人： FUJITSU LIMITED

发明人： Fukumura, Hiromi ,  Suga, Katsuya

IPC分类号： G06F13/16 ,  G06F1/32 ,  G06F11/10 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F1/3275 ,  G06F11/106 ,  G06F13/1657 ,  G06F13/1668 ,  Y02D10/13 ,  Y02D10/14

摘要： A disclosed information processing apparatus includes: one or plural memories, each of which includes a self-refresh function; and a memory control unit that stops a patrol that includes reading and error correction with respect to a memory among the one or plural memories, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories.

公开(公告)号：EP2498163A2

公开(公告)日：2012-09-12

申请号：EP12158299.3

申请日：2012-03-06

申请人： Fujitsu Limited

发明人： Okano, Kenji ,  Gotsubo, Kenji ,  Yamada, Tadashi ,  Fukumura, Hiromi

IPC分类号： G06F1/14

CPC分类号： G06F1/14

摘要： In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.

摘要翻译： 在信息处理装置中，控制单元包括用于提供一天中的时间的第一时钟装置。 物理域包括第二时钟设备，并且实现用作虚拟信息处理设备的逻辑域。 控制单元控制第一时钟装置与第二时钟装置的时间之间的第一时间差。 物理域控制第二时钟设备和逻辑域的时间之间的第二时间差。 在信息处理设备中，基于第一和第二时间差异来控制逻辑域上的时间。