公开(公告)号：EP0297821A3

公开(公告)日：1990-02-07

申请号：EP88305857.0

申请日：1988-06-28

申请人： FUJITSU LIMITED

发明人： Kawata, Mitsuya

IPC分类号： G01R31/26 ,  G11C11/34 ,  G11C29/00

CPC分类号： G11C29/12 ,  G11C29/54

摘要： A semiconductor integrated circuit device has a normal mode and a test mode for testing a memory thereof, and comprises input/output buffer parts (15, 16) having input/output terminals, at least one gate array (10, 11), at least one memory (12, 13), a first interconnection (18a-18d) for coupling the input/output buffer parts, the gate array and the memory and routed depending on a logic operation to be carried out by the semiconductor integrated circuit, and a second inter­connection (17) for coupling the input/output buffer parts, the gate array and the memory, where the second interconnection is fixed regardless of the logic operation to be carried out by the semiconductor integrated circuit. The input/output buffer parts comprise a first input/output part (15₁, ...) having a first terminal (15P) which is used in common as an input terminal of the first interconnection for receiving a normal input signal in the normal mode and an input terminal of the second interconnection for receiving a test signal in the test mode, and a second input/output part (16₁, ...) having a second terminal (22) which is used in common as an output terminal of the first interconnection and an output terminal of the second interconnection.

公开(公告)号：EP0297821A2

公开(公告)日：1989-01-04

申请号：EP88305857.0

申请日：1988-06-28

申请人： FUJITSU LIMITED

发明人： Kawata, Mitsuya

IPC分类号： G01R31/26 ,  G11C11/34 ,  G11C29/00

CPC分类号： G11C29/12 ,  G11C29/54

摘要： A semiconductor integrated circuit device has a normal mode and a test mode for testing a memory thereof, and comprises input/output buffer parts (15, 16) having input/output terminals, at least one gate array (10, 11), at least one memory (12, 13), a first interconnection (18a-18d) for coupling the input/output buffer parts, the gate array and the memory and routed depending on a logic operation to be carried out by the semiconductor integrated circuit, and a second inter­connection (17) for coupling the input/output buffer parts, the gate array and the memory, where the second interconnection is fixed regardless of the logic operation to be carried out by the semiconductor integrated circuit. The input/output buffer parts comprise a first input/output part (15₁, ...) having a first terminal (15P) which is used in common as an input terminal of the first interconnection for receiving a normal input signal in the normal mode and an input terminal of the second interconnection for receiving a test signal in the test mode, and a second input/output part (16₁, ...) having a second terminal (22) which is used in common as an output terminal of the first interconnection and an output terminal of the second interconnection.

摘要翻译： 半导体集成电路器件具有用于测试其存储器的正常模式和测试模式，并且包括具有输入/输出端子的输入/输出缓冲器部分（15,16），至少一个门阵列（10,11） 一个存储器（12,13），用于耦合输入/输出缓冲器部分，门阵列和存储器并根据要由半导体集成电路执行的逻辑操作来路由的第一互连（18a-18d），以及 第二互连（17），用于耦合输入/输出缓冲器部分，门阵列和存储器，其中第二互连是固定的，而与由半导体集成电路执行的逻辑操作无关。 输入/输出缓冲器部分包括具有第一端子（15P）的第一输入/输出部分（151），其被共同用作第一互连的输入端子，用于在正常模式下接收正常输入信号 以及用于在测试模式中接收测试信号的第二互连的输入端，以及具有第二端子（22）的第二输入/输出部分（161），其被共同地用作所述测试模式的输出端子 第一互连和第二互连的输出端。