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1.发明授权
公开(公告)号：EP3719804B1
公开(公告)日：2024-07-10
申请号：EP20153300.7
申请日：2020-01-23
IPC分类号： G11C29/24 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/48 , G11C29/50 , G11C29/54 , G11C29/56 , G11C11/413 , G11C11/417
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2.发明公开STATIC RANDOM ACCESS MEMORY (SRAM) ARRAYS HAVING SUBSTANTIALLY CONSTANT OPERATIONAL PERFORMANCE ACROSS MULTIPLE MODES OF OPERATION 审中-公开静态随机存取存储器（SRAM）阵列在多种操作模式下具有大致恒定的运行性能
公开(公告)号：EP3271921A1
公开(公告)日：2018-01-24
申请号：EP16711416.4
申请日：2016-03-01
发明人： MOJUMDER, Niladri, Narayan , LIU, Ping , SONG, Stanley, Seungchul , WANG, Zhongze , YEAP, Choh, Fei
IPC分类号： G11C11/413 , G11C11/417 , G11C11/419 , G11C29/02 , G11C29/54
CPC分类号： G11C11/417 , G06F17/5068 , G11C11/412 , G11C11/413 , G11C11/419 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/54 , G11C2029/1202 , G11C2029/1204
摘要： Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.
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3.发明公开System and method for automatically testing integrated circuit memory arrays on different memory array testers 失效用于自动测试不同存储器阵列测试仪的集成电路存储器阵列的系统和方法
公开(公告)号：EP0135864A3
公开(公告)日：1988-04-20
申请号：EP84110538
申请日：1984-09-05
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , F02B2075/027 , G01R31/318342 , G01R31/31908 , G11C29/54
摘要： A system for automatically testing a plurality of memory arrays (25A... 25X) on selected memory array testers (21A... 21X) includes an interactive data entry device (12) for entering array test specifications (20A...20N) including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator (14) generates a tester independent universal language instruction sequence (16) for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a language translator (19A... 19X) which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester (21A ... 21X). The tester dependent instruction sequence (30A ... 30X) may be loaded into the associated tester to produce the test signals for testing the memory array (25A... 25X).
摘要翻译： 用于自动测试所选择的存储器阵列测试仪上的多个存储器阵列的系统包括用于输入阵列测试规范的交互式数据输入装置，包括阵列的特征信息，DC测试参数，AC测试参数和AC测试模式选择。 测试规格以独立于特定测试仪特性的格式输入。 通用语言生成器生成测试仪独立的通用语言指令序列，用于根据输入的测试规范执行规定的测试。 与每个测试器相关联的是通用语言翻译器，其将测试仪独立的通用语言指令序列转换成相关测试仪特有的指令序列。 测试仪相关指令序列可以被加载到相关联的测试器中以产生用于测试存储器阵列的测试信号。
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4.发明公开
公开(公告)号：EP1756739A4
公开(公告)日：2008-03-12
申请号：EP05706055
申请日：2005-01-20
申请人： NEC LAB AMERICA INC
发明人： GANAI MALAY , GUPTA AARTI , ASHAR PRANAV N
CPC分类号： G11C29/54 , G06F17/504 , G11C2029/0401
摘要： A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.
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公开(公告)号：EP0297821A3
公开(公告)日：1990-02-07
申请号：EP88305857.0
申请日：1988-06-28
申请人： FUJITSU LIMITED
发明人： Kawata, Mitsuya
摘要： A semiconductor integrated circuit device has a normal mode and a test mode for testing a memory thereof, and comprises input/output buffer parts (15, 16) having input/output terminals, at least one gate array (10, 11), at least one memory (12, 13), a first interconnection (18a-18d) for coupling the input/output buffer parts, the gate array and the memory and routed depending on a logic operation to be carried out by the semiconductor integrated circuit, and a second interconnection (17) for coupling the input/output buffer parts, the gate array and the memory, where the second interconnection is fixed regardless of the logic operation to be carried out by the semiconductor integrated circuit. The input/output buffer parts comprise a first input/output part (15₁, ...) having a first terminal (15P) which is used in common as an input terminal of the first interconnection for receiving a normal input signal in the normal mode and an input terminal of the second interconnection for receiving a test signal in the test mode, and a second input/output part (16₁, ...) having a second terminal (22) which is used in common as an output terminal of the first interconnection and an output terminal of the second interconnection.
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6.发明公开Testing integrated circuits with fault dictionary 审中-公开测试von integrierten Schaltungen mit Fehler-Wörterbuch
公开(公告)号：EP1480227A1
公开(公告)日：2004-11-24
申请号：EP03101472.3
申请日：2003-05-22
IPC分类号： G11C29/00
摘要： A method and apparatus for diagnosing resistive open defects in address decoders and, in particular memory address decoders. The method and apparatus accelerate the diagnosis process of detecting any resistive open defects that may occur during production, particularly where time-to market is a very important factor. Based on the disclosed invention, many actions for improving yield can be taken. In accordance with the invention, there is created a fault dictionary of resistive-open defects based on defect location, transistor types, terminal names and also the fault behavior. The dictionary enhances the diagnosing capabilities and also helps in differentiating between resistive bridge and resistive open defects.
摘要翻译： 一种用于诊断地址解码器中的电阻开路缺陷的方法和装置，特别是存储器地址解码器。 该方法和设备加速了在生产过程中可能出现的任何电阻性开放缺陷的诊断过程，特别是上市时间是非常重要的因素。 基于所公开的发明，可以采取许多用于提高产量的动作。 根据本发明，基于缺陷位置，晶体管类型，终端名称以及故障行为创建了电阻开放缺陷的故障字典。 字典增强诊断能力，也有助于区分电阻桥和电阻开路缺陷。
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7.发明公开System and method for automatically testing integrated circuit memory arrays on different memory array testers 失效用于自动系统和方法的测试构造对存储器阵列不同审查员集成电路存储器阵列。
公开(公告)号：EP0135864A2
公开(公告)日：1985-04-03
申请号：EP84110538.0
申请日：1984-09-05
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , F02B2075/027 , G01R31/318342 , G01R31/31908 , G11C29/54
摘要： A system for automatically testing a plurality of memory arrays (25A... 25X) on selected memory array testers (21A... 21X) includes an interactive data entry device (12) for entering array test specifications (20A...20N) including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator (14) generates a tester independent universal language instruction sequence (16) for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a language translator (19A... 19X) which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester (21A ... 21X). The tester dependent instruction sequence (30A ... 30X) may be loaded into the associated tester to produce the test signals for testing the memory array (25A... 25X).
摘要翻译： 一种用于选择的存储器阵列上的自动测试存储器阵列的所述多个系统包括测试者交互式数据输入装置用于输入阵列测试规范，包括表征信息，DC检测参数，AC测试参数和用于阵列AC测试图案的选择。 测试规范中设定的格式全部是独立的特定测试的特征输入。 一种通用语言生成基因费率进行基于输入的测试规范规定的测试的测试器独立的通用语言指令序列。 每个测试器相关联是一种通用语言翻译其中反式鲈测试仪独立通用语言指令序列到在所有的指令序列是特别相关的测试。 该测试器相关的指令序列可以被加载到相关联的测试仪，以产生测试信号用于测试存储器阵列。
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公开(公告)号：EP4362024A3
公开(公告)日：2024-07-31
申请号：EP24164272.7
申请日：2019-04-16
IPC分类号： G01R31/317 , G06F12/14 , G06F9/22 , G06F21/44 , G06F21/60 , G06F21/78 , G06F21/62 , G06F21/71 , G11C7/24 , G11C29/48 , G11C29/54 , G11C29/56 , G11C29/04 , G11C29/44
CPC分类号： G06F21/71 , G06F21/6209 , G11C29/56016 , G11C2029/040320130101 , G11C7/24 , G11C2029/440220130101 , G11C29/48 , G11C29/54 , G01R31/31719 , G06F12/1408 , G06F12/1458 , G06F2212/105220130101 , G06F21/608 , G06F21/44 , G06F2221/214320130101 , G06F2221/03320130101 , G06F21/78
摘要： An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.
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公开(公告)号：EP4362024A2
公开(公告)日：2024-05-01
申请号：EP24164272.7
申请日：2019-04-16
IPC分类号： G11C29/44
CPC分类号： G06F21/71 , G06F21/6209 , G11C29/56016 , G11C2029/040320130101 , G11C7/24 , G11C2029/440220130101 , G11C29/48 , G11C29/54 , G01R31/31719 , G06F12/1408 , G06F12/1458 , G06F2212/105220130101 , G06F21/608 , G06F21/44 , G06F2221/214320130101 , G06F2221/03320130101 , G06F21/78
摘要： An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.
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10.发明公开
公开(公告)号：EP1756739A2
公开(公告)日：2007-02-28
申请号：EP05706055.0
申请日：2005-01-20
发明人： GANAI, Malay , GUPTA, Aarti , ASHAR, Pranav, N.
IPC分类号： G06F17/50
CPC分类号： G11C29/54 , G06F17/504 , G11C2029/0401
摘要： A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.
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