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    Semiconductor memory device
    1.
    发明公开
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：EP1246200A2

    公开(公告)日：2002-10-02

    申请号：EP01310201.7

    申请日：2001-12-05

    申请人： FUJITSU LIMITED

    发明人： Yagishita, Yoshimasa, c/o Fujitsu Limited ,  Uchida, Toshiya, c/o Fujitsu Limited

    IPC分类号： G11C29/00

    CPC分类号： G11C29/80 ,  G11C29/848

    摘要： A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

    摘要翻译： 一种半导体存储器件，可降低布线处罚的可能性。 地址输入电路接收地址信号输入。 驱动电路根据地址信号驱动存储器阵列。 信号线连接地址输入电路和驱动电路。 冗余电路位于驱动电路附近，并将包括冗余线的其他线替换为存储器阵列中的缺陷线。 缺陷行信息存储电路存储表示缺陷行的信息。 供电电路通过信号线将存储在有缺陷线信息存储电路中的信息提供给冗余电路。 该结构使得能够通过公共信号线发送地址信号和关于缺陷线的信息，并且减少布线的数量和布线处罚的可能性。

    Semiconductor memory device
    3.
    发明公开
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：EP1246194A2

    公开(公告)日：2002-10-02

    申请号：EP01309750.6

    申请日：2001-11-20

    申请人： FUJITSU LIMITED

    发明人： Yagishita, Yoshimasa, c/o Fujitsu Limited ,  Uchida, Toshiya, c/o Fujitsu Limited

    IPC分类号： G11C11/406

    CPC分类号： G11C11/406 ,  G11C7/1006 ,  G11C11/4096 ,  G11C2211/4062

    摘要： A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block.

    摘要翻译： 即使在刷新操作期间也允许访问并且功耗低的半导体存储器件。 地址输入电路接收输入地址，并且读出电路从经由地址输入电路输入的地址指定的列或行方向上排列的子块组的至少一部分读出数据。 刷新电路刷新排列在行或列方向上的子块组的至少一部分，并且与由读出电路从其读出数据的子块组交叉。 数据恢复电路参考来自其他子块和奇偶校验块的数据，恢复同时发生刷新操作和读出操作的子块的数据。

    Methods for operating semiconductor memory devices and semiconductor memory devices
    5.
    发明公开
    Methods for operating semiconductor memory devices and semiconductor memory devices 有权
    Halbleiterspeicheranordnungen und ihre Betriebsverfahren

    公开(公告)号：EP1050882A2

    公开(公告)日：2000-11-08

    申请号：EP00303775.1

    申请日：2000-05-05

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Takaaki, c/o Fujitsu Limited ,  Uchida, Toshiya, c/o Fujitsu Limited ,  Sato, Kotoku, c/o Fujitsu Limited ,  Yagishita, Yoshimasa, c/o Fujitsu Limited

    IPC分类号： G11C5/06

    CPC分类号： G11C11/406 ,  G11C5/066 ,  G11C11/40603 ,  G11C11/40611

    摘要： A semiconductor memory device having a plurality of operating modes for controlling an internal circuit comprises a command controlling circuit which accepts signals supplied to predetermined terminals as commands at a plurality of times. The number of operating modes is sequentially narrowed down based on each command and the internal circuit is controlled according to the narrowed operating modes. One such command controlling circuit comprises a plurality of accepting circuits (94a). Each of the accepting circuits (94a) respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit (94a) is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.
    Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.

    摘要翻译： 具有用于控制内部电路的多个操作模式的半导体存储器件包括命令控制电路，其接受作为命令多次提供给预定端子的信号。 基于每个命令，操作模式的数量依次变窄，并且根据变窄的操作模式来控制内部电路。 一个这样的指令控制电路包括多个接受电路（94a）。 每个接受电路（94a）分别接收每次多次提供的信号。 换句话说，根据信号补充的定时，分别操作不同的接受电路（94a），并且控制内部电路。 因此，即使在具有复杂的指令组合的半导体存储器件中，命令控制电路也可以容易地设计。 因此，它能够方便验证设计。 由于多次接受确定操作模式所需的信息，因此可以减少输入命令所需的终端数量。 特别地，在专用端子输入命令的情况下，不再需要其输入焊盘，输入电路等，从而可以减小芯片尺寸。 通过减少端子数量来实现减少，这限制了封装尺寸。