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    IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
    3.
    发明公开
    IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION 审中-公开
    内部检测低位改进的更新速率基于效绩的系统

    公开(公告)号：EP2939239A1

    公开(公告)日：2015-11-04

    申请号：EP13868489.9

    申请日：2013-06-24

    申请人： Intel Corporation

    发明人： SCHOENBORN, Theodore Z. ,  MOZAK, Christopher P.

    IPC分类号： G11C11/406 ,  G11C11/402

    CPC分类号： G11C7/02 ,  G11C11/40 ,  G11C11/40611 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  G11C2211/4062

    摘要： A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.

    MEMORY DEVICE AND REFRESH ADJUSTING METHOD
    5.
    发明公开
    MEMORY DEVICE AND REFRESH ADJUSTING METHOD 有权
    澳大利亚证券交易所

    公开(公告)号：EP2075706A1

    公开(公告)日：2009-07-01

    申请号：EP06821972.4

    申请日：2006-10-20

    申请人： Fujitsu Limited

    发明人： SASAKI, Takatsugu

    IPC分类号： G06F12/16 ,  G11C11/401

    CPC分类号： G11C11/406 ,  G06F11/106 ,  G11C2211/4062

    摘要： When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T1 of a refresh request generating unit to T2 and causes a patrol controlling unit to intensively carry out an error patrol of an error-occurred address at a cycle T3, which is slightly longer than the changed refresh cycle T2. If an error is not detected for more than a predetermined period of time after the error patrol is started, the error patrol is stopped. Furthermore, if a single error is not detected for more than a predetermined period of time after the error patrol is stopped, the shortening of the refresh cycle is cancelled and returned to the original cycle.

    摘要翻译： 当通过ECC电路检测到数据的单个错误时，设置在存储器板上的循环调整单元将刷新请求生成单元的刷新周期T1缩短到T2，并且使巡视控制单元集中地执行错误巡检 在比更新的刷新周期T2稍长的周期T3的错误发生的地址。 如果在错误巡视开始之后没有检测到超过预定时间段的错误，则错误巡视停止。 此外，如果在错误巡视停止之后没有检测到大于预定时间段的单个错误，则刷新周期的缩短被取消并返回到原始周期。

    SEMICONDUCTOR MEMORY AND OPERATION METHOD OF SEMICONDUCTOR MEMORY
    10.
    发明公开
    SEMICONDUCTOR MEMORY AND OPERATION METHOD OF SEMICONDUCTOR MEMORY 有权
    HERBLEITERSPEICHER UND VERFAHREN ZUM BETRIEB EINES HALBLEITERSPEICHERS

    公开(公告)号：EP1657723A1

    公开(公告)日：2006-05-17

    申请号：EP03818115.2

    申请日：2003-08-18

    申请人： FUJITSU LIMITED

    发明人： ETO, Satoshi, c/o FUJITSU LIMITED

    IPC分类号： G11C29/00 ,  G11C11/401

    CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C29/52 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

    摘要： A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects an error for each read data string, and sets the most reliable result of the error detection results to be true. The error correction circuit decodes data to be read from the refresh block based on a true error detection result. Moreover, the error correction circuit corrects the error of the read data string corresponding to the true error detection result. Consequently, without extending the read cycle time, a refresh operation can be hid, and an error can be corrected simultaneously. By correcting a data error read from a bad memory cell of data retention characteristics, a refresh request interval can be extended, and power consumption during a standby period can be reduced.

    摘要翻译： 数据附加电路分别将从刷新块读取的多种期望数据分别添加到从其他块读取的数据，以产生多个读取数据串。 纠错电路检测每个读取数据串的错误，并将错误检测结果的最可靠结果设置为真。 误差校正电路根据真实的误差检测结果对从刷新块读出的数据进行解码。 此外，纠错电路校正与真实错误检测结果相对应的读取数据串的错误。 因此，不延长读周期时间，可以隐藏刷新操作，并且可以同时校正错误。 通过校正从不良存储单元读取的数据保留特性的数据错误，可以扩展刷新请求间隔，并且可以减少待机期间的功耗。