公开(公告)号：EP2229730B1

公开(公告)日：2013-04-24

申请号：EP07849357.4

申请日：2007-12-06

Applicant: Freescale Semiconductor, Inc.

Inventor： ROTH, Andreas ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  LEHMANN, Stephan ,  WITTICH, Engelbert

IPC: H03K17/0814 ,  H03K19/003

CPC classification number: H03K19/00346 ,  G06F21/755

公开(公告)号：EP2229730A1

公开(公告)日：2010-09-22

申请号：EP07849357.4

申请日：2007-12-06

Applicant: Freescale Semiconductor, Inc.

Inventor： ROTH, Andreas ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  LEHMANN, Stephan ,  WITTICH, Engelbert

IPC: H03K17/0814 ,  H03K19/003

CPC classification number: H03K19/00346 ,  G06F21/755

Abstract: A semiconductor device includes a substrate (1) on which an electronic circuit (40) is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter (50) is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit (60) is connected to the current meter (50) and the electronic circuit (40), for controlling the electronic circuit based on the measured parameter.

公开(公告)号：EP2158677A1

公开(公告)日：2010-03-03

申请号：EP07789692.6

申请日：2007-06-14

Applicant: Freescale Semiconductor, Inc.

Inventor： BODE, Hubert ,  LAUDENBACH, Andreas ,  ROTH, Andreas ,  WITTICH, Engelbert

IPC: H03K5/1252 ,  H03K5/156

CPC classification number: H03K5/1252

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.