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1572 条记录 (耗时 0.019 秒)

    DRIVER CIRCUIT RECEIVING A REGULATED PRE-DRIVER SUPPLY VOLTAGE
    3.
    发明公开
    DRIVER CIRCUIT RECEIVING A REGULATED PRE-DRIVER SUPPLY VOLTAGE 审中-公开
    控制电路，用于接收稳压电源先行控制

    公开(公告)号：EP3089368A2

    公开(公告)日：2016-11-02

    申请号：EP16165753.1

    申请日：2016-04-18

    申请人： Freescale Semiconductor, Inc.

    发明人： Sanchez, Hector

    IPC分类号： H03K19/0185 ,  H03K19/003

    CPC分类号： H03K19/018521 ,  H03K19/00361 ,  H03K19/00384

    摘要： A driver circuit (200) includes first (215) and second (225) pluralities of series-connected inverters for pre-driving an input signal (IN) to first and second drive transistors (224, 234) , and a plurality of capacitors (250-258). The first and second drive transistors (224, 234) coupled to the last inverter of the first (22) and second (232) pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment (fig. 3), a plurality of discharge circuits (328-334) is coupled to the first plurality of series-connected inverters (311). Another embodiment (fig. 4) includes a combination of capacitors 468-480 and discharge circuits (470-474, 4802-486) coupled to the first plurality of series-connected inverters (411). The embodiments (fig. 2, 3, 4) provide a driver circuit (224, 234 or 354, 364 or 454, 464) with high frequency voltage regulation (at regulated volatge Vddo, Vssr).

    摘要翻译： 的驱动电路（200）包括第一（215）和第二（225）串联连接的反相器的输入信号的预驱动（IN）的多个第一和第二驱动晶体管（224，234），和电容器的多个（ 250-258）。 耦合到第一（22）的负载反相器和串联连接的逆变器的第二（232）的多个第一和第二驱动器晶体管（224，234）。 耦合的反相器相应的一系列连接的反相器的第一和第二多个的输出端子之间的电容器的多个每个电容器。 在另一个实施例（图3），放电电路的多个（328-334）耦合到串联连接的反相器（311）的所述第一多个。 另一个实施例（图4）包括电容器468-480以及耦合到串联连接的反相器（411）的所述第一多个放电电路（470-474，4802-486）的组合。 的实施例（图2，3，4）提供的驱动器电路（224，234或354，364或454，464）与高频电压调节（在调节volatge VDDO，VSSR）。

    METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTOR DEVICES
    4.
    发明公开
    METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTOR DEVICES 有权
    VERFAHREN ZUR HERSTELLUNGEBENENÜBERGREIFENDERDIELEKTRISCHER STRUKTUREN AUF HALBLEITERBAUELEMENTEN

    公开(公告)号：EP3082161A1

    公开(公告)日：2016-10-19

    申请号：EP16165360.5

    申请日：2016-04-14

    申请人： Freescale Semiconductor, Inc.

    发明人： Reber, Douglas ,  Shroff, Mehul

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/7688 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/53295

    摘要： A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor (304) and the second conductor (306), removing patterned material to form an air gap (402) between the first conductor and the second conductor, applying a self-supporting film (404), preferably graphene or silicene, on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

    摘要翻译： 提供半导体器件和制造半导体器件的方法。 制造半导体器件的方法可以包括图案化用于第一导体和第二导体的层，电镀图案化部分的层以形成第一导体（304）和第二导体（306），去除图案化材料以形成空气 在第一导体和第二导体之间的间隙（402），在第一导体和第二导体的顶部上施加自支撑膜（404），优选石墨烯或硅，以封闭气隙，并使自支撑 导致自支撑膜基本上不导电的膜。

    BANDWIDTH ESTIMATION CIRCUIT, COMPUTER SYSTEM, METHOD FOR ESTIMATING AND PREDICTING THE BANDWIDTH AND COMPUTER READABLE PROGRAM PRODUCT
    5.
    发明公开
    BANDWIDTH ESTIMATION CIRCUIT, COMPUTER SYSTEM, METHOD FOR ESTIMATING AND PREDICTING THE BANDWIDTH AND COMPUTER READABLE PROGRAM PRODUCT 审中-公开
    带宽估计电路，计算机系统中，用于估计和预测的带宽和计算机可读程序产品

    公开(公告)号：EP3077885A1

    公开(公告)日：2016-10-12

    申请号：EP13898775.5

    申请日：2013-12-05

    申请人： Freescale Semiconductor, Inc.

    发明人： KRUTSCH, Robert Cristian ,  GANCEV, Valentin-Adrian

    IPC分类号： G06F1/00

    摘要： The present invention relates to a bandwidth estimation circuit for estimating and predicting the bandwidth of a computer system, the bandwidth estimation circuit comprising: a memory unit which is configured to store multiple predetermined bandwidth envelopes, wherein each one of the predetermined bandwidth envelopes is assigned to a feature of a code of an application program; a bandwidth measurement unit which is configured to online measure the bandwidth of a data transaction based on the code; a selection unit coupled either to the memory unit and the bandwidth measurement unit and configured to find the nearest bandwidth envelopes in the memory unit for the measured bandwidth; a calculation unit which is configured to calculate a ratio between the selected bandwidth envelopes, to construct a new bandwidth envelope by applying an interpolation function based on the calculated ratio and to calculate an estimated bandwidth by applying the new bandwidth envelope. The present invention also relates to a computer system, a method for estimating and predicting the bandwidth and a computer readable program product.

    DATA PROCESSING SYSTEM WITH TEMPERATURE MONITORING FOR SECURITY
    6.
    发明公开
    DATA PROCESSING SYSTEM WITH TEMPERATURE MONITORING FOR SECURITY 审中-公开
    DATENVERARBEITUNGSSYSTEM MITTEMPERATURÜBERWACHUNGFÜRSICHERHEIT

    公开(公告)号：EP3073412A1

    公开(公告)日：2016-09-28

    申请号：EP16161724.6

    申请日：2016-03-22

    申请人： Freescale Semiconductor, Inc.

    发明人： ARORA, Mohit ,  MCQUIRK, Dale ,  BHARGAVA, Prashant ,  GALLIMORE, Simon ,  SEABERG, Charles

    IPC分类号： G06F21/86

    CPC分类号： G06F21/86 ,  G01K3/005 ,  G01R31/31719 ,  G06F21/71 ,  G06F21/755 ,  G06F21/81

    摘要： A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

    摘要翻译： 处理系统包括处理器和温度安全模块，其被耦合以向处理器提供温度篡改信号。 温度安全模块包括搁板模式修整值，操作模式修整值和可编程温度修剪值。 基于处理系统的部署模式来设置温度监视器修整值，可以使用可编程温度修正值，搁架模式修整值和操作模式修整值之一。

    Reducing MEMS stiction by deposition of nanoclusters
    7.
    发明授权
    Reducing MEMS stiction by deposition of nanoclusters 有权
    责任的减少MEMS通过纳米团簇沉积

    公开(公告)号：EP2746218B1

    公开(公告)日：2016-09-28

    申请号：EP13196317.5

    申请日：2013-12-09

    申请人： Freescale Semiconductor, Inc.

    发明人： Steimle, Robert F. ,  Montez, Ruben B.

    IPC分类号： B81B3/00

    CPC分类号： B81B3/001 ,  B81B3/0005 ,  B81B2201/0221 ,  B81B2201/0235 ,  B81B2203/0181 ,  B81B2203/06 ,  B81C1/0096 ,  B81C2201/115 ,  G01P15/0802 ,  G01P2015/0871 ,  G01P2015/0874

    摘要： A method for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters (520). When a next portion of the MEMS device is formed on the sacrificial layer (810), this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface (910) decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.

    DATA PROCESSOR HAVING MULTIPLE LOW POWER MODES
    10.
    发明公开
    DATA PROCESSOR HAVING MULTIPLE LOW POWER MODES 有权
    具有多NIEDRIGLEISTUNGSMODI数据处理器

    公开(公告)号：EP2577422A4

    公开(公告)日：2016-08-10

    申请号：EP11787069

    申请日：2011-04-20

    申请人： FREESCALE SEMICONDUCTOR INC

    发明人： RAMARAJU RAVINDRARAJ ,  BEARDEN DAVID R ,  COOPER TROY L

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/171

    摘要： A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.