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公开(公告)号：EP0079531A2
公开(公告)日：1983-05-25
申请号：EP82110163.1
申请日：1982-11-04
IPC分类号： G06F15/68
摘要： A method of controlling a digital video processor in a digital fluorography system wherein the electronic components of the processor are variously configured to perform math functions and manipulations on digital image data obtained in connection with carrying out x-ray examination procedures and the images are displayed on a television monitor or recorded. A system controller sends a complete recipe for a procedure to the memory of a microprocessor based CPU that controls the video processor. The latter CPU interprets the instructions and effects configurations and reconfigurations in the data paths of the video processor during television vertical blanking intervals.
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3.发明公开Data switching for combined bus and star data network 失效Datenvermittlungfürkombiniertes Bus- und Sternnetzwerk。
公开(公告)号：EP0226963A2
公开(公告)日：1987-07-01
申请号：EP86117254.2
申请日：1986-12-11
CPC分类号： H04L12/28
摘要： A dual-data-rate bus system employs a first data rate in a star bus system external to a data switch a higher data rate on a bus internal to the data switch. The internal data rate is selected high enough to permit simultaneous data communication between all suitable pairs of external nodes without data loss. In the preferred embodiment, external communication between the data switch and external nodes employs carrier-sense, multiple-access, with collision detection and the internal bus employs parallel communication with polling or token passing. The internal data rate is at least n/2 times the data rate of each external link, where n is the number of external links. In a further embodiment, the internal bus employs serial carrier-sense, multiple-access, with collision detection operating at a data rate at least 10 percent greater than n/2 times the data rate of each external link.
摘要翻译： 双数据速率总线系统在数据交换机外部的星形总线系统中采用第一数据速率，在数据交换机内部的总线上采用更高的数据速率。 内部数据速率被选择得足够高以允许在所有合适的外部节点对之间同时进行数据通信而没有数据丢失。 在优选实施例中，数据交换机和外部节点之间的外部通信采用具有冲突检测的载波侦听多路访问，并且内部总线采用与轮询或令牌通过的并行通信。 内部数据速率至少为每个外部链路的数据速率的n / 2倍，其中n是外部链路的数量。 在另一个实施例中，内部总线采用串行载波检测多路访问，其中冲突检测以比每个外部链路的数据速率的n / 2倍大至少10％的数据速率操作。
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4.发明公开Network interface equipment for interfacing digital data with a bus network 失效用于数字数据的适配到总线网络的网络接口设备。
公开(公告)号：EP0226975A2
公开(公告)日：1987-07-01
申请号：EP86117321.9
申请日：1986-12-12
CPC分类号： H04L12/40032 , G06F13/128 , H04L12/4015 , H04L12/413
摘要： A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.
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公开(公告)号：EP0079531A3
公开(公告)日：1985-03-27
申请号：EP82110163
申请日：1982-11-04
IPC分类号： G06F15/20
摘要： A method of controlling a digital video processor in a digital fluorography system wherein the electronic components of the processor are variously configured to perform math functions and manipulations on digital image data obtained in connection with carrying out x-ray examination procedures and the images are displayed on a television monitor or recorded. A system controller sends a complete recipe for a procedure to the memory of a microprocessor based CPU that controls the video processor. The latter CPU interprets the instructions and effects configurations and reconfigurations in the data paths of the video processor during television vertical blanking intervals.
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6.发明公开Network interface equipment for interfacing digital data with a bus network 失效用于将数字数据与总线网络接口的网络接口设备
公开(公告)号：EP0226975A3
公开(公告)日：1989-09-27
申请号：EP86117321.9
申请日：1986-12-12
CPC分类号： H04L12/40032 , G06F13/128 , H04L12/4015 , H04L12/413
摘要： A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.
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公开(公告)号：EP0226963A3
公开(公告)日：1989-08-30
申请号：EP86117254.2
申请日：1986-12-11
CPC分类号： H04L12/28
摘要： A dual-data-rate bus system employs a first data rate in a star bus system external to a data switch a higher data rate on a bus internal to the data switch. The internal data rate is selected high enough to permit simultaneous data communication between all suitable pairs of external nodes without data loss. In the preferred embodiment, external communication between the data switch and external nodes employs carrier-sense, multiple-access, with collision detection and the internal bus employs parallel communication with polling or token passing. The internal data rate is at least n/2 times the data rate of each external link, where n is the number of external links. In a further embodiment, the internal bus employs serial carrier-sense, multiple-access, with collision detection operating at a data rate at least 10 percent greater than n/2 times the data rate of each external link.
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