公开(公告)号：EP0730220A2

公开(公告)日：1996-09-04

申请号：EP96103171.3

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Savkar, Sunil W.

IPC分类号： G06F9/32

CPC分类号： G06F9/324 ,  G06F9/322

摘要： A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode. The target address of the relative control transfer instruction is determined by using, incrementing or decrementing, depending on the state of the flags, a group of the most significant bits from the relative control transfer instruction address and appending the result with the least significant bits from the result of the addition described above.

摘要翻译： 一种方法和装置接受相对控制传输指令，并产生紧凑的绝对控制传送指令，该指令可以具有比相对控制传送指令大一位的位数，并且包括用于快速构建相对控制传送指令的目标地址的标志。 紧凑的绝对控制传送指令是通过扩展相对控制传送指令的位移并将其从控制传送指令地址添加到一组最低有效位的符号来生成的，并且可选地将结果中的一些或全部位与 原始操作码或不同的操作码。 相对控制传送指令的目标地址是根据标志的状态通过使用，递增或递减来确定的，来自相对控制传送指令地址的最高有效位组，并将结果与​​最低有效位相加 上述添加的结果。

公开(公告)号：EP0730221A2

公开(公告)日：1996-09-04

申请号：EP96103172.1

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Katsuno, Akira ,  Savkar, Sunil W. ,  Shebanow, Michael C.

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30127 ,  G06F9/4486

摘要： The present invention provides a method of accelerating the return from program flow changes in the execution of a program containing a plurality of instructions. The method includes the step of fetching a program flow change and determining if the program flow change contains a return instruction. A value a value of a program counter is registered that identifies a location in the program for the return from the program flow change. The program flow change is executed. A predicted value is speculated from a return prediction table and the program flow change returns in accordance with the speculative value.

摘要翻译： 本发明提供了一种在包含多个指令的程序的执行中加速程序流程改变返回的方法。 该方法包括获取程序流程改变并确定程序流程改变是否包含返回指令的步骤。 注册程序计数器的值的值，其识别程序中用于从程序流程更改返回的位置。 执行程序流程更改。 从返回预测表推测出预测值，并根据推测值返回程序流程。

公开(公告)号：EP0730221A3

公开(公告)日：1997-05-14

申请号：EP96103172.1

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Katsuno, Akira ,  Savkar, Sunil W. ,  Shebanow, Michael C.

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30127 ,  G06F9/4486

摘要： The present invention provides a method of accelerating the return from program flow changes in the execution of a program containing a plurality of instructions. The method includes the step of fetching a program flow change and determining if the program flow change contains a return instruction. A value a value of a program counter is registered that identifies a location in the program for the return from the program flow change. The program flow change is executed. A predicted value is speculated from a return prediction table and the program flow change returns in accordance with the speculative value.

公开(公告)号：EP0730220A3

公开(公告)日：1997-01-08

申请号：EP96103171.3

申请日：1996-03-01

申请人： HAL COMPUTER SYSTEMS, INC.

发明人： Savkar, Sunil W.

IPC分类号： G06F9/32

CPC分类号： G06F9/324 ,  G06F9/322

摘要： A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode. The target address of the relative control transfer instruction is determined by using, incrementing or decrementing, depending on the state of the flags, a group of the most significant bits from the relative control transfer instruction address and appending the result with the least significant bits from the result of the addition described above.