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    Integrated circuit air bridge structures and methods of fabricating same
    2.
    发明公开
    Integrated circuit air bridge structures and methods of fabricating same 失效
    Halbleiterelement mitLuftbrückenstrukturund deren Herstellungsverfahren

    公开(公告)号：EP0812016A1

    公开(公告)日：1997-12-10

    申请号：EP97108480.1

    申请日：1997-05-26

    申请人： HARRIS CORPORATION

    发明人： Begley, Patrick A. ,  Rivoli, Anthony L. ,  Young, William R. ,  Delgado, Jose A. ,  Gaul, Stephen J.

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/3205

    CPC分类号： H01L28/10 ,  H01L21/7682 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Conductive elements may be incorporated in the devices at the integrated circuit level. An elongated conductor is formed over the dielectric layer and is encased in dielectric material. Then, portions of the substrate or the dielectric layer, or both, are removed to expose the encased elongated conductor to air. The method contemplates using sacrificial materials located between the encased conductor in the substrate. Removing the sacrificial material forms an air bridge cavity. The methods of the invention also include removing portions of the substrate in order to form the air bridge cavity. In a bonded substrate structure, a device substrate is bonded to a handle substrate, typically with an oxide bonding layer. Trench isolation is a common step used in the formation of devices and bonded substrates. The air bridge of the invention is compatible with the trench forming steps that are typically used in bonded substrates. In one bonded substrate embodiment, trenches are formed down to the oxide bonding layer. The trenches are coated with a dielectric, filled, and planarized. The dielectric layer covers the planarized trenches and elongated conductors are patterned on the dielectric layer over the air bridge trenches. Another dielectric layer covers the patterned conductors in order to encase them in a dielectric. Then the substrate is further patterned and etched to remove material from between the filled air bridge trenches. The final structure provides air bridge conductors encased in a dielectric that is spaced from the bonding oxide layer.

    摘要翻译： 导电元件可以集成在集成电路级的器件中。 细长的导体形成在电介质层之上，并被封装在电介质材料中。 然后，去除衬底或电介质层的一部分或两者，以将包裹的细长导体暴露于空气。 该方法考虑使用位于衬底中的封装导体之间的牺牲材料。 去除牺牲材料形成空气桥腔。 本发明的方法还包括去除基板的部分以形成空气桥腔。 在键合衬底结构中，器件衬底通常用氧化物结合层结合到处理衬底上。 沟槽隔离是用于形成器件和键合衬底的常用步骤。 本发明的空气桥与通常用于粘合的基底中的沟槽形成步骤兼容。 在一个键合衬底的实施例中，沟槽形成到氧化物结合层下方。 沟槽涂有电介质，填充和平面化。 电介质层覆盖平坦化的沟槽，细长导体在空气桥沟上的介电层上图案化。 另一个电介质层覆盖图案化的导体，以便将它们封装在电介质中。 然后进一步图案化和蚀刻衬底以从填充的空气桥接沟槽之间移除材料。 最终结构提供封装在与结合氧化物层间隔开的电介质中的空气桥导体。

    Plural-bit recoding multiplier
    5.
    发明公开
    Plural-bit recoding multiplier 失效
    多位重新编码乘法器

    公开(公告)号：EP0428942A3

    公开(公告)日：1993-02-03

    申请号：EP90121386.8

    申请日：1990-11-08

    申请人： HARRIS CORPORATION

    发明人： Young, William R. ,  Malinowski, Christopher W.

    IPC分类号： G06F7/52 ,  G06F7/544 ,  G06F15/31

    CPC分类号： G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/5443

    摘要： A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats. The principles are also applied to multiplier/accumulators and complex multipliers.

    摘要翻译： 两个或更多位组的重新编码方法，以减少部分产品的数量及其硬件实现。 独特的补充方案，补充载体的预先添加以及符号扩展的衍生也减少了硬件实现，并允许乘法器处理输入和输出格式的任意组合。 这些原则也适用于乘法器/累加器和复数乘法器。

    Plural-bit recoding multiplier
    6.
    发明公开
    Plural-bit recoding multiplier 失效
    Mehrere Bit umkodierender Multiplizierer。

    公开(公告)号：EP0428942A2

    公开(公告)日：1991-05-29

    申请号：EP90121386.8

    申请日：1990-11-08

    申请人： HARRIS CORPORATION

    发明人： Young, William R. ,  Malinowski, Christopher W.

    IPC分类号： G06F7/52 ,  G06F7/544 ,  G06F15/31

    CPC分类号： G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/5443

    摘要： A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats. The principles are also applied to multiplier/accumulators and complex multipliers.

    摘要翻译： 一种用于减少部分产品数量及其硬件实现的两个或多个位组的重新编码方法。 独特的补充方案，补充载体的预加载和符号扩展的推导也减少了硬件实现，并允许乘法器处理输入和输出格式的任何组合。 这些原理也适用于乘法器/累加器和复数乘法器。