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1.发明公开NANOSCALE SHIFT REGISTER AND SIGNAL DEMULTIPLEXING USING MICROSCALE/NANOSCALE SHIFT REGISTERS 有权纳米级移位寄存器和SIGNALDEMULTIPLEXEN使用MIKROMASSSTAB- /纳米尺度滑动寄存器
公开(公告)号：EP1938332A1
公开(公告)日：2008-07-02
申请号：EP06788135.9
申请日：2006-07-21
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires (1011-1017) of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches (1030-1037), each series controlled by common latch-control signals. Internal latches of each series of latches (1030-1033) are alternatively interconnected with a previous lacth of the other series (1034-1037) and a next latch of the other series by two series of gates (1023, 1025, 1027, 1029, 1022,1024, 1026, 1028), each controlled by a gate signal line (1006 and 1004).
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2.发明授权NANOSCALE SHIFT REGISTER AND SIGNAL DEMULTIPLEXING USING MICROSCALE/NANOSCALE SHIFT REGISTERS 有权纳米级移位寄存器和SIGNALDEMULTIPLEXEN使用MIKROMASSSTAB- /纳米尺度滑动寄存器
公开(公告)号：EP1938332B1
公开(公告)日：2011-10-19
申请号：EP06788135.9
申请日：2006-07-21
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires (1011-1017) of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches (1030-1037), each series controlled by common latch-control signals. Internal latches of each series of latches (1030-1033) are alternatively interconnected with a previous lacth of the other series (1034-1037) and a next latch of the other series by two series of gates (1023, 1025, 1027, 1029, 1022,1024, 1026, 1028), each controlled by a gate signal line (1006 and 1004).
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公开(公告)号：EP1588376B1
公开(公告)日：2007-09-12
申请号：EP04785812.1
申请日：2004-01-27
发明人： KUEKES, Philip J,
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/02 , G11C2213/77 , G11C2213/81 , Y10S977/94
摘要： A molecular crossbar latch is provided, comprising two control wires and a signal wire that crosses the two control wires to form a junction with each control wire. The latch further includes a control mechanism for controllably electrically connecting and disconnecting signal input to the latch, thus allowing the input to change its logic value after the signal is latched while the signal wire retains its latched value. Each junction forms a switch, the junction having a functional dimension in nanometers. The crossbar latch permits latching a logic value on the signal wire. Further, methods are provided for latching logic values in a logic array, for inventing a logic value , and for restoring a voltage value of a signal in a nano-scale wire.
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公开(公告)号：EP2020030A2
公开(公告)日：2009-02-04
申请号：EP07777247.3
申请日：2007-05-22
IPC分类号： H01L27/06
CPC分类号： H01L27/0688 , H01L21/8221 , H01L2924/00011 , H01L2924/0002 , H01L2924/00012 , H01L2224/80001
摘要： An embodiment of an integrated circuit comprises active components in more than one active layer. A first conductor (26, 310, 366) in one active layer (22, 304, 360) is operative to produce a static electric field that controls a first active element in an adjacent active layer (30, 320).
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公开(公告)号：EP1500110B1
公开(公告)日：2007-06-13
申请号：EP03721635.5
申请日：2003-04-11
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0014 , G11C13/0023 , G11C2213/75 , G11C2213/77 , G11C2213/81 , H01L27/285 , H01L51/0052 , H01L51/0595 , Y10S977/943
摘要： A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.
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公开(公告)号：EP1588376A2
公开(公告)日：2005-10-26
申请号：EP04785812.1
申请日：2004-01-27
发明人： KUEKES, Philip J,
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/02 , G11C2213/77 , G11C2213/81 , Y10S977/94
摘要： A molecular crossbar latch is provided, comprising two control wires and a signal wire that crosses the two control wires to form a junction with each control wire. The latch further includes a control mechanism for controllably electrically connecting and disconnecting signal input to the latch, thus allowing the input to change its logic value after the signal is latched while the signal wire retains its latched value. Each junction forms a switch, the junction having a functional dimension in nanometers. The crossbar latch permits latching a logic value on the signal wire. Further, methods are provided for latching logic values in a logic array, for inventing a logic value , and for restoring a voltage value of a signal in a nano-scale wire.
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公开(公告)号：EP1500110A1
公开(公告)日：2005-01-26
申请号：EP03721635.5
申请日：2003-04-11
IPC分类号： G11C16/04
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0014 , G11C13/0023 , G11C2213/75 , G11C2213/77 , G11C2213/81 , H01L27/285 , H01L51/0052 , H01L51/0595 , Y10S977/943
摘要： A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.
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