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    A processor with cache memory used in receiving data from other processors
    2.
    发明公开
    A processor with cache memory used in receiving data from other processors 失效
    Prozessor und Cache-Speicher zum Empfang von Daten anderer Prozessoren。

    公开(公告)号：EP0588369A1

    公开(公告)日：1994-03-23

    申请号：EP93115106.2

    申请日：1993-09-20

    申请人： HITACHI, LTD.

    发明人： Higuchi, Tatsuo ,  Hamanaka, Naoki

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0813

    摘要： A processor (1) for a multiprocessor system, such as a parallel processor system, connected to a network (2) has a sending unit (11) and a receiving unit (12) for transferring and receiving data to and from the network (2) as well as receive cache (22) and main cache. When data are received from the network (2), it is determined whether a hit or miss occurs to the main cache (21) and receive cache (22), respectively. If a hit to the receive cache (22) occurs, then the receive cache controller (14) stores the data directly in the receive cache (22) as it is received. When a hit to the main cache (21) occurs, an intercache transfer is executed for transferring the hit block in the main cache (21) to the receive cache (22) so that the data can be stored in the receive cache (22). When an instruction processor (10) requests access to data held in the receive cache (22), the data are retrieved to the instruction processor (10) and at the same time transferred to the main cache (21).

    摘要翻译： 用于连接到网络（2）的诸如并行处理器系统的多处理器系统的处理器（1）具有发送单元（11）和用于从网络（2）传送和接收数据的发送单元（11）和接收单元（12） ）以及接收缓存（22）和主缓存。 当从网络（2）接收到数据时，确定是否发生命中或未命中到主缓存（21）和接收缓存（22）。 如果发生对接收缓存（22）的命中，则接收高速缓存控制器（14）在接收高速缓存（22）中直接存储数据。 当发生对主缓存（21）的命中时，执行中间传送以将主缓存（21）中的命中块传送到接收缓存（22），使得数据可以存储在接收缓存（22）中， 。 当指令处理器（10）请求对接收高速缓存（22）中保存的数据的访问时，将数据检索到指令处理器（10）并同时传送到主缓存器（21）。

    A computer system
    6.
    发明公开
    A computer system 失效
    Ein Rechnersystem。

    公开(公告)号：EP0674276A1

    公开(公告)日：1995-09-27

    申请号：EP95104390.0

    申请日：1995-03-24

    申请人： HITACHI, LTD.

    发明人： Hamilton, Patrick ,  Nakagoshi, Junji ,  Higuchi, Tatsuo ,  Ando, Toshimitsu ,  Iwasaki, Masaaki

    IPC分类号： G06F15/16

    CPC分类号： G06F15/17 ,  G06F13/24

    摘要： To reduce the overhead of the interrupt on a processor (103) associated with packet send and receive control in a network (102), packet send command chaining means is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor (103) in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor (103) is caused for each packet send and receive operation.

    摘要翻译： 为了减少与网络（102）中的分组发送和接收控制相关联的处理器（103）上的中断的开销，提供分组发送命令链接装置。 基于每个分组发送命令中的控制字段，发送节点在分组级别中控制对处理器（103）的中断请求，并将具有控制信息的分组发送到接收节点。 接收节点根据接收到的数据包中的控制字段来控制接收电路中断请求，从而减少每个数据包发送和接收操作引起指令处理器（103）中断的次数。