公开(公告)号：EP0591695B1

公开(公告)日：1998-02-11

申请号：EP93114493.5

申请日：1993-09-09

申请人： HITACHI, LTD.

发明人： Uchiyama, Kunio ,  Nishii, Osamu

IPC分类号： G11C8/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

公开(公告)号：EP0404128B1

公开(公告)日：1997-09-03

申请号：EP90111694.7

申请日：1990-06-20

申请人： HITACHI, LTD. ,  HITACHI VLSI ENGINEERING CORPORATION

发明人： Nishii, Osamu ,  Uchiyama, Kunio ,  Aoki, Hirokazu ,  Kikuchi, Takashi ,  Saigou, Yasuhiko

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0897

公开(公告)号：EP0412353A2

公开(公告)日：1991-02-13

申请号：EP90114195.2

申请日：1990-07-24

申请人： HITACHI, LTD.

发明人： Nishii, Osamu ,  Uchiyama, Kunio ,  Aoki, Hirokazu ,  Oishi, Kanji ,  Kitano, Jun ,  Hatano, Susumu

IPC分类号： G06F12/08

CPC分类号： G06F12/0833

摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating sig­nal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relat­ing to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

摘要翻译： 在本发明公开的多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器：地址总线（123），数据总线（126）上（100 2＃1和＃），以无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓冲存储器是由复录方法操作。 （：＃1 100）存在于从包括一个无效的第一状态下，一个有效的和非更新的第二状态，并有效的和更新的第三状态中选择的一个状态中的第一高速缓存的数据的状态。 第二高速缓存（100＃2）被构造像第一高速缓存中。 当第一处理器的写访问命中所述第一高速缓存中，第一高速缓存的数据的状态从所述第二状态转换到第三状态，并且第一高速缓存输出写入命中的地址和无效信号到 地址总线和无效信号线，分别。 当从第一处理器的写访问未命中的第一高速缓存中，一个块的数据是块转移从主存储器到所述第一高速缓存和无效信号的输出。 在此之后，第一高速缓存执行在传输块中的数据的写入。 在情况下，第一和第二高速缓存在第三状态与相关的地址时，处理的访问请求被馈送到地址总线（123）保持的数据，相关的高速缓存在主存储器写回恰当的数据。

公开(公告)号：EP0809252B1

公开(公告)日：2003-11-26

申请号：EP97112849.1

申请日：1993-09-09

申请人： Hitachi, Ltd.

发明人： Uchiyama, Kunio ,  Nishii, Osamu

IPC分类号： G11C8/00 ,  H04N7/00 ,  G06F15/78

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

公开(公告)号：EP0809252A3

公开(公告)日：1998-04-01

申请号：EP97112849.1

申请日：1993-09-09

申请人： HITACHI, LTD.

发明人： Uchiyama, Kunio ,  Nishii, Osamu

IPC分类号： G11C8/00 ,  H04N7/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： The data processing system preferably employs standard components with general applicability in different architectures. A single chip main storage apparatus (102) is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode. Another chip comprises a microprocessor unit (101) and a main storage controller (104) which are respectively formed of independent cores inside the same chip. The microprocessor unit (101), the main storage controller (104) and the main storage apparatus (102) are coupled together by buses (153, 154). A control bus (156) supplies control signals from the main storage controller (104) to the main storage apparatus (102). Timing control for the data processing system is through a clock generator (103) which supplies synchronous clock signals to the microprocessor unit (101) via coupling line (150), to the main storage controller (104) via coupling line (152), and to the main storage apparatus (102) via coupling line (151). Circuitry to enable the control of parallel accesses to a plurality of memory banks in the main storage apparatus (102) and of setting an operation mode function to a mode register built in said synchronous dynamic memory is arranged in the main storage controller (104) so that both the conventional microprocessor unit (101) and the conventional main storage apparatus (104) are not burdened with special circuitry which would impair the use of processor IC cores and memory IC chips of standard design and high generality.

公开(公告)号：EP0404128A2

公开(公告)日：1990-12-27

申请号：EP90111694.7

申请日：1990-06-20

申请人： HITACHI, LTD. ,  HITACHI VLSI ENGINEERING CORPORATION

发明人： Nishii, Osamu ,  Uchiyama, Kunio ,  Aoki, Hirokazu ,  Kikuchi, Takashi ,  Saigou, Yasuhiko

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0897

摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has a multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to be transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated either as a copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbable for the address of access for writing to conflict with a signal on the bidirectional connection.

摘要翻译： 在多处理器系统中相对于外部和内部高速缓存的非共享系统具有多层分层缓存。 主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。 无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的 被发送到主存储器地址总线31，因为外部高速缓存12,22被操作为复制回写或一次写入系统。 结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能 在双向连接上有一个信号。

公开(公告)号：EP0383097A2

公开(公告)日：1990-08-22

申请号：EP90101908.3

申请日：1990-01-31

申请人： HITACHI, LTD. ,  HITACHI VLSI ENGINEERING CORPORATION

发明人： Saigou, Yasuhiko ,  Fukuta, Hiroshi ,  Kikuchi, Takashi ,  Konoma, Toshihiko ,  Nagashima, Osamu ,  Uchiyama, Kunio ,  Aoki, Hirokazu ,  Nishii, Osamu ,  Oishi, Kanji ,  Kitano, Jun ,  Hatano, Susumu

IPC分类号： G06F12/08

CPC分类号： G06F12/0253 ,  G06F12/0835

摘要： A cache memory is connected to the microprocessor via a MPU bus and to the main memory via a memory bus. The data transfer between the main memory and the data memory DTM of the cache memory is executed block by block via the buffer memory BM. The directory memory DLM holds, as address tags, the high-order bits of the main memory addresses of the data stored in the data memory DTM. A tag comparator TCP compares an address tag stored in the directory memory DLM with the address tag derived from the MPU-bus and produces a signal CH which indicates a coindicende (cache-hit) or a non-coincidence (mis-hit). In the case of a cache-hit, a data transfer is executed between the microprocessor and the data memory DTM instead of the main memory.
The cache memory has a function of monitoring any address change in the main memory due to a dynamic relocation or garbage collection e.g. The address change implies a data-°­transfer start address and a data-transfer end address.
In case of an address change in the main memory, the cache memory automatically updates the internal address tag in conformity with the data-transfer start and end address.

摘要翻译： 高速缓冲存储器经由MPU总线连接到微处理器，并通过存储器总线连接到主存储器。 高速缓冲存储器的主存储器和数据存储器DTM之间的数据传输通过缓冲存储器BM逐块执行。 目录存储器DLM作为地址标签保存存储在数据存储器DTM中的数据的主存储器地址的高位。 标签比较器TCP将存储在目录存储器DLM中的地址标签与从MPU总线导出的地址标签进行比较，并产生指示coindicende（高速缓存命中）或不重合（mis-hit）的信号CH。 在高速缓存命中的情况下，在微处理器和数据存储器DTM而不是主存储器之间执行数据传送。 缓存存储器具有监视由于动态重定位或垃圾收集而导致的主存储器中的任何地址变化的功能。 地址改变意味着数据传输开始地址和数据传输结束地址。 在主存储器中更改地址的情况下，高速缓冲存储器将自动更新内部地址标签，符合数据传输开始和结束地址。

公开(公告)号：EP0809252A2

公开(公告)日：1997-11-26

申请号：EP97112849.1

申请日：1993-09-09

申请人： HITACHI, LTD.

发明人： Uchiyama, Kunio ,  Nishii, Osamu

IPC分类号： G11C8/00 ,  H04N7/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： The data processing system preferably employs standard components with general applicability in different architectures. A single chip main storage apparatus (102) is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode. Another chip comprises a microprocessor unit (101) and a main storage controller (104) which are respectively formed of independent cores inside the same chip. The microprocessor unit (101), the main storage controller (104) and the main storage apparatus (102) are coupled together by buses (153, 154). A control bus (156) supplies control signals from the main storage controller (104) to the main storage apparatus (102). Timing control for the data processing system is through a clock generator (103) which supplies synchronous clock signals to the microprocessor unit (101) via coupling line (150), to the main storage controller (104) via coupling line (152), and to the main storage apparatus (102) via coupling line (151). Circuitry to enable the control of parallel accesses to a plurality of memory banks in the main storage apparatus (102) and of setting an operation mode function to a mode register built in said synchronous dynamic memory is arranged in the main storage controller (104) so that both the conventional microprocessor unit (101) and the conventional main storage apparatus (104) are not burdened with special circuitry which would impair the use of processor IC cores and memory IC chips of standard design and high generality.

摘要翻译： 数据处理系统优选地采用在不同架构中具有普遍适用性的标准组件。 单芯片主存储装置（102）是具有多个存储体的同步动态存储器和用于确定操作模式的模式寄存器。 另一芯片包括分别由同一芯片内的独立核心形成的微处理器单元（101）和主存储控制器（104）。 微处理器单元（101），主存储控制器（104）和主存储设备（102）通过总线（153,154）耦合在一起。 控制总线（156）将来自主存储控制器（104）的控制信号提供给主存储装置（102）。 数据处理系统的定时控制是通过时钟发生器（103），其通过耦合线路（150）向微处理器单元（101）提供同步时钟信号，经由耦合线路（152）提供给主存储控制器（104），以及 经由耦合线路（151）向主存储装置（102）发送。 在主存储控制器（104）中布置有用于控制对主存储装置（102）中的多个存储体的并行访问的控制以及将操作模式功能设置为内置于所述同步动态存储器中的模式寄存器的电路 传统的微处理器单元（101）和传统的主存储设备（104）都不会受到损害标准设计和高通用性的处理器IC内核和存储器IC芯片的使用的特殊电路的负担。

公开(公告)号：EP0591695A1

公开(公告)日：1994-04-13

申请号：EP93114493.5

申请日：1993-09-09

申请人： HITACHI, LTD.

发明人： Uchiyama, Kunio ,  Nishii, Osamu

IPC分类号： G11C8/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A main storage apparatus (102) is a synchronous dynamic memory (501) having a plurality of memory banks (502, 503) and a mode register (505) for determining an operation mode, a main storage controller (104) is coupled to a processor (101) and the main storage apparatus (102), and means to realize controlling of parallel access to a plurality of banks (502, 503) of the memory (501) and controlling of setting of an operation mode to the built-in register (505) is arranged in the main storage controller (104). Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

摘要翻译： 主存储装置（102）是具有用于确定操作模式的多个存储体（502,503）和模式寄存器（505）的同步动态存储器（501），主存储控制器（104）耦合到 处理器（101）和主存储装置（102），以及用于实现对存储器（501）的多个存储体（502,503）的并行访问的控制以及将操作模式设置为内置的装置 寄存器（505）布置在主存储控制器（104）中。 因此，可以确保使用高通用性和常规存储器的常规处理器。

公开(公告)号：EP0412353A3

公开(公告)日：1992-05-27

申请号：EP90114195.2

申请日：1990-07-24

申请人： HITACHI, LTD.

发明人： Nishii, Osamu ,  Uchiyama, Kunio ,  Aoki, Hirokazu ,  Oishi, Kanji ,  Kitano, Jun ,  Hatano, Susumu

IPC分类号： G06F12/08

CPC分类号： G06F12/0833

摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating sig­nal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relat­ing to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.