公开(公告)号：EP0418505A2

公开(公告)日：1991-03-27

申请号：EP90114193.7

申请日：1990-07-24

申请人： HITACHI, LTD.

发明人： Sagara, Kazuhiko ,  Itoh, Kiyoo ,  Kitsukawa, Goro ,  Kawamoto, Yoshifumi ,  Kawajiri, Yoshiki

IPC分类号： H01L21/82

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/10817 ,  Y10S148/144

摘要： Sources and drains (14, 15) of MOS transistors are formed after the formation of an emitter (10) of a bipolar transis­tor, whereby the sources and drains are made smaller in thick­ness than the emitter (10, xjE). Since the sources and drains (14, 15) are not subjected to a high-temperature heat treat­ment conducted in the formation of the emitter (10), there is no fear of increase in thickness (xj(nMOS), xj(pMOS)) of the sources and drains (14, 15) caused by the diffusion of impuri­ties. There can be formed a BiCMOS having a high integration density and superior characteristics.

摘要翻译： 在形成双极晶体管的发射极（10）之后形成MOS晶体管的源极和漏极（14,15），由此使源极和漏极的厚度比发射极（10，xjE）更小。 由于源极和漏极（14,15）不经受在发射极（10）的形成中进行的高温热处理，所以不用担心厚度增加（xj（nMOS），xj（pMOS））） 由杂质扩散引起的污水源（14,15）。 可以形成具有高集成度和优异特性的BiCMOS。

公开(公告)号：EP0111651B1

公开(公告)日：1989-08-09

申请号：EP83109585.6

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

公开(公告)号：EP0182067B1

公开(公告)日：1992-01-15

申请号：EP85112753.0

申请日：1985-10-08

申请人： HITACHI, LTD.

发明人： Sagara, Kazuhiko ,  Nakamura, Tohru ,  Nakazato, Kazuo ,  Kure, Tokuo ,  Ikeda, Kiyoji ,  Homma, Noriyuki

IPC分类号： H01L27/10

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

公开(公告)号：EP0182067A2

公开(公告)日：1986-05-28

申请号：EP85112753.0

申请日：1985-10-08

申请人： HITACHI, LTD.

发明人： Sagara, Kazuhiko ,  Nakamura, Tohru ,  Nakazato, Kazuo ,  Kure, Tokuo ,  Ikeda, Kiyoji ,  Homma, Noriyuki

IPC分类号： H01L27/10

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

摘要： A semiconductor device includes a layer (3) doped with impurities, provided between a buried layer (2) and an epitaxial layer (4), and having a conductivity of the type opposite to that of said buried layer (2) and said epitaxial layer (4). A reversely biasing voltage is applied across the buried layer (2) and the doped layer (3). Side surfaces of the epitaxial layer (4) are surrounded by an insulator (7).
This helps effectively to prevent any element (10...14) formed in the epitaxial layer (4) from being affected by a-particles and greatly improves the reliability of the semiconductor device.

公开(公告)号：EP0111651A2

公开(公告)日：1984-06-27

申请号：EP83109585.6

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

摘要： Devices formed in a semiconductor integrated circuit device are electrically isolated by a pair of narrow and deep grooves (9), thick oxide films (14) formed on the surfaces of the grooves and a thick oxide film (15) formed on a surface of an area between the grooves.

摘要翻译： 形成在半导体集成电路器件中的器件通过一对窄沟槽和深沟槽（9），形成在沟槽表面上的厚氧化膜（14）和形成在沟槽表面上的厚氧化膜（15）电隔离， 凹槽之间的区域。

公开(公告)号：EP0418505A3

公开(公告)日：1991-09-25

申请号：EP90114193.7

申请日：1990-07-24

申请人： HITACHI, LTD.

发明人： Sagara, Kazuhiko ,  Itoh, Kiyoo ,  Kitsukawa, Goro ,  Kawamoto, Yoshifumi ,  Kawajiri, Yoshiki

IPC分类号： H01L21/82

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/10817 ,  Y10S148/144

摘要： Sources and drains (14, 15) of MOS transistors are formed after the formation of an emitter (10) of a bipolar transis­tor, whereby the sources and drains are made smaller in thick­ness than the emitter (10, xjE). Since the sources and drains (14, 15) are not subjected to a high-temperature heat treat­ment conducted in the formation of the emitter (10), there is no fear of increase in thickness (xj(nMOS), xj(pMOS)) of the sources and drains (14, 15) caused by the diffusion of impuri­ties. There can be formed a BiCMOS having a high integration density and superior characteristics.

公开(公告)号：EP0182067A3

公开(公告)日：1987-08-12

申请号：EP85112753

申请日：1985-10-08

申请人： HITACHI, LTD.

发明人： Sagara, Kazuhiko ,  Nakamura, Tohru ,  Nakazato, Kazuo ,  Kure, Tokuo ,  Ikeda, Kiyoji ,  Homma, Noriyuki

IPC分类号： H01L27/10

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

摘要： A semiconductor device includes a layer (3) doped with impurities, provided between a buried layer (2) and an epitaxial layer (4), and having a conductivity of the type opposite to that of said buried layer (2) and said epitaxial layer (4). A reversely biasing voltage is applied across the buried layer (2) and the doped layer (3). Side surfaces of the epitaxial layer (4) are surrounded by an insulator (7). This helps effectively to prevent any element (10...14) formed in the epitaxial layer (4) from being affected by a-particles and greatly improves the reliability of the semiconductor device.

公开(公告)号：EP0111651A3

公开(公告)日：1986-02-05

申请号：EP83109585

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

摘要： Devices formed in a semiconductor integrated circuit device are electrically isolated by a pair of narrow and deep grooves (9), thick oxide films (14) formed on the surfaces of the grooves and a thick oxide film (15) formed on a surface of an area between the grooves.