公开(公告)号：EP0097326A1

公开(公告)日：1984-01-04

申请号：EP83105880.5

申请日：1983-06-15

申请人： HITACHI, LTD.

发明人： Yamamoto, Syuichi ,  Hashimoto, Norikazu ,  Sasaki, Toshio ,  Masuhara, Toshiaki ,  Minato, Osamu ,  Tamaki, Yoichi ,  Hayashida, Tetsuya

IPC分类号： H01L21/76 ,  H01L27/08

CPC分类号： H01L21/76224 ,  H01L21/76202 ,  H01L27/0921

摘要： To the ends of avoiding an abnormal phenomenon such as latch-up attributed to a parasitic element and of enhancing the density of integration, a groove-like insulator layer (20) extending in the depthwise direction of a semiconductor body (1) is formed at a boundary part between a well region (2) and the semiconductor body (1). Owing to the insulator layer (20), conductive regions which would constitute the parasitic element are separated apart, so that the latch-up phenomenon does not arise. Therefore, the area of the well region (2) can be made small, and the density of integration can be made 1.4 times higher than in prior-art LSI circuits.

摘要翻译： 为了避免归因于寄生元件的闩锁的异常现象和增强集成密度的结束，在半导体本体（1）的深度方向上延伸的槽状绝缘体层（20）形成在 阱区域（2）和半导体本体（1）之间的边界部分。 由于绝缘体层（20），将构成寄生元件的导电区域分开，使得不会产生闭锁现象。 因此，可以使阱区域（2）的面积小，并且集成度可以比现有技术的LSI电路高1.4倍。

公开(公告)号：EP0097326B1

公开(公告)日：1987-01-28

申请号：EP83105880.5

申请日：1983-06-15

申请人： HITACHI, LTD.

发明人： Yamamoto, Syuichi ,  Hashimoto, Norikazu ,  Sasaki, Toshio ,  Masuhara, Toshiaki ,  Minato, Osamu ,  Tamaki, Yoichi ,  Hayashida, Tetsuya

IPC分类号： H01L21/76 ,  H01L27/08

CPC分类号： H01L21/76224 ,  H01L21/76202 ,  H01L27/0921

公开(公告)号：EP0111651A2

公开(公告)日：1984-06-27

申请号：EP83109585.6

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

摘要： Devices formed in a semiconductor integrated circuit device are electrically isolated by a pair of narrow and deep grooves (9), thick oxide films (14) formed on the surfaces of the grooves and a thick oxide film (15) formed on a surface of an area between the grooves.

摘要翻译： 形成在半导体集成电路器件中的器件通过一对窄沟槽和深沟槽（9），形成在沟槽表面上的厚氧化膜（14）和形成在沟槽表面上的厚氧化膜（15）电隔离， 凹槽之间的区域。

公开(公告)号：EP0111651B1

公开(公告)日：1989-08-09

申请号：EP83109585.6

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

公开(公告)号：EP0068679B1

公开(公告)日：1987-11-11

申请号：EP82302975.6

申请日：1982-06-09

申请人： Hitachi, Ltd.

发明人： Tamaki, Yoichi ,  Kure, Tokuo ,  Shiba, Takeo ,  Higuchi, Hisayuki

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L21/31056 ,  H01L21/306 ,  H01L21/32134 ,  H01L21/763

公开(公告)号：EP0048175B1

公开(公告)日：1986-04-23

申请号：EP81304255.3

申请日：1981-09-16

申请人： Hitachi, Ltd.

发明人： Tamaki, Yoichi ,  Kure, Tokuo ,  Sato, Akira ,  Higuchi, Hisayuki

IPC分类号： H01L21/76 ,  H01L27/04

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/161 ,  Y10S148/168

公开(公告)号：EP0068679A2

公开(公告)日：1983-01-05

申请号：EP82302975.6

申请日：1982-06-09

申请人： Hitachi, Ltd.

发明人： Tamaki, Yoichi ,  Kure, Tokuo ,  Shiba, Takeo ,  Higuchi, Hisayuki

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L21/31056 ,  H01L21/306 ,  H01L21/32134 ,  H01L21/763

摘要： After filling isolation grooves (12) with a filling material (15), this filling material is etched by the use of a double-layer film (16, 17) which is made of substances different from each other.
Side etching of the lower film (16) of the double-layer film and etching of the filling material (15) are alternately performed in such a manner that each etching is carried out two or more times. Thus, the upper surface of the filling material contained in each groove can be flattened, to improve the reliability of wiring formed over the upper surface.

公开(公告)号：EP0111651A3

公开(公告)日：1986-02-05

申请号：EP83109585

申请日：1983-09-26

申请人： HITACHI, LTD.

发明人： Tamaki, Yoichi ,  Shiba, Takeo ,  Sagara, Kazuhiko ,  Kawamura, Masao

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/763

摘要： Devices formed in a semiconductor integrated circuit device are electrically isolated by a pair of narrow and deep grooves (9), thick oxide films (14) formed on the surfaces of the grooves and a thick oxide film (15) formed on a surface of an area between the grooves.

公开(公告)号：EP0068679A3

公开(公告)日：1984-07-25

申请号：EP82302975

申请日：1982-06-09

申请人： Hitachi, Ltd.

发明人： Tamaki, Yoichi ,  Kure, Tokuo ,  Shiba, Takeo ,  Higuchi, Hisayuki

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L21/31056 ,  H01L21/306 ,  H01L21/32134 ,  H01L21/763

摘要： After filling isolation grooves (12) with a filling material (15), this filling material is etched by the use of a double-layer film (16, 17) which is made of substances different from each other. Side etching of the lower film (16) of the double-layer film and etching of the filling material (15) are alternately performed in such a manner that each etching is carried out two or more times. Thus, the upper surface of the filling material contained in each groove can be flattened, to improve the reliability of wiring formed over the upper surface.

公开(公告)号：EP0048175A3

公开(公告)日：1982-11-10

申请号：EP81304255

申请日：1981-09-16

申请人： Hitachi, Ltd.

发明人： Tamaki, Yoichi ,  Kure, Tokuo ,  Sato, Akira ,  Higuchi, Hisayuki

IPC分类号： H01L21/76 ,  H01L27/04

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/161 ,  Y10S148/168

摘要： A semiconductor device has a plurality of elements isolated by a groove (10) which is at least partly filled with insulating material. To avoid risk of breakage of conductive layers later formed on the groove, the groove has a gentle slope (17) at its upper side wall portions, and a steep slope (18) at its lower side wall portions. This groove (10) provides gentle steps at its mouth but occupies small area on the substrate (1), thus enabling an extremely high-density integrated circuit to be formed.