A control device for controlling a controlled apparatus, and a control method therefor
    2.
    发明公开
    A control device for controlling a controlled apparatus, and a control method therefor 失效
    一种用于控制受控系统及其控制方法的控制装置。

    公开(公告)号:EP0460892A2

    公开(公告)日:1991-12-11

    申请号:EP91304997.9

    申请日:1991-06-03

    申请人: HITACHI, LTD.

    摘要: In order to control an apparatus (1), such as a rolling mill, a control device (4) may use a pre-set operation pattern to generate a pre-set command signal, which is then modified.
    That first modification may be part of a feedback loop (Fig. 33) in dependence on the variation of a variable operation device (2) of the apparatus (1), on a plurality of pre-set signals may be combined by fuzzy logic (Fig. 29). Then the relationship between the modified pre-set command signal and the variation of the variable operation device (2) is investigated to generate a compensation signal which is used to modify further the pre-set command signal. In a feedback loop (Fig. 33), that further modification may compensate for changes in the operating point of the loop, due to changes in the apparatus (1) being controlled. In a fuzzy logic arrangement (Fig. 29), the compensation signal may be a further control pattern developed by the control device (4) itself, which is combined with the pre-set patterns by fuzzy logic. The control device may be in the form of a series of modules (375, 379).

    摘要翻译: 为了控制(1)的设备,包括:如轧机,控制装置(4)可以使用预先设定的操作模式,以生成预先设定的指令信号,在所有其然后修改。 该第一变形例可以是反馈回路的一部分(图33)(在(2)上的装置(1),在预先设定的信号的多元性可通过模糊逻辑组合的可变操作装置的变化的依赖 图29)。 然后修改的预先设定的指令信号和操作可变装置(2)的变化之间的关系进行了研究,以产生补偿信号的所有其用于进一步修改预设指令信号。 在反馈回路中(图33),没有进一步的修改可以补偿环路的工作点的变化,由于在(1)被控制的装置的变化。 在一个模糊逻辑装置(图29),该补偿信号可以是由所述控制装置开发的另外的控制模式(4)本身,所有这一切都与由模糊逻辑预先设定的图案结合。 该控制装置可以是一系列模块(375,379)的形式。

    Data transmission bus system for a plurality of processors
    5.
    发明公开
    Data transmission bus system for a plurality of processors 失效
    Datenübertragungsbussystemfürmehrere Prozessoren。

    公开(公告)号:EP0076494A2

    公开(公告)日:1983-04-13

    申请号:EP82109102.2

    申请日:1982-10-01

    申请人: Hitachi, Ltd.

    IPC分类号: G06F13/00 G06F15/16

    CPC分类号: G06F15/161 G06F13/366

    摘要: A data transmission system for transferring data between a plurality of processors (200A - 200G, 200Z, 2000) and between the processors and an input/output unit (303) through a common bus (301) has linkage units (300A - 300G, 300Z, 300L) between the processors and the bus and an address controller (302) to manage the bus. Each of the linkage units has a two-port random access memory (42A - 42G) for storing data necessary for the processor. The processor processes the data stored in the memory and writes a result of the processing in an output area of the memory. The processing of the processors and the data transfer through the bus are essentially separated and carried out independently.

    摘要翻译: 用于通过公共总线(301)在多个处理器(200A-200G,200Z,2000)之间以及处理器与输入/输出单元(303)之间传送数据的数据传输系统具有连接单元(300A-300G,300Z ,300L)和地址控制器(302)之间,用于管理总线。 每个联动单元具有用于存储处理器所需的数据的双端口随机存取存储器(42A-42G)。 处理器处理存储在存储器中的数据,并将处理结果写入存储器的输出区域。 处理器的处理和通过总线的数据传输基本上是分开的,并且是独立执行的。