公开(公告)号：EP0097326A1

公开(公告)日：1984-01-04

申请号：EP83105880.5

申请日：1983-06-15

申请人： HITACHI, LTD.

发明人： Yamamoto, Syuichi ,  Hashimoto, Norikazu ,  Sasaki, Toshio ,  Masuhara, Toshiaki ,  Minato, Osamu ,  Tamaki, Yoichi ,  Hayashida, Tetsuya

IPC分类号： H01L21/76 ,  H01L27/08

CPC分类号： H01L21/76224 ,  H01L21/76202 ,  H01L27/0921

摘要： To the ends of avoiding an abnormal phenomenon such as latch-up attributed to a parasitic element and of enhancing the density of integration, a groove-like insulator layer (20) extending in the depthwise direction of a semiconductor body (1) is formed at a boundary part between a well region (2) and the semiconductor body (1). Owing to the insulator layer (20), conductive regions which would constitute the parasitic element are separated apart, so that the latch-up phenomenon does not arise. Therefore, the area of the well region (2) can be made small, and the density of integration can be made 1.4 times higher than in prior-art LSI circuits.

摘要翻译： 为了避免归因于寄生元件的闩锁的异常现象和增强集成密度的结束，在半导体本体（1）的深度方向上延伸的槽状绝缘体层（20）形成在 阱区域（2）和半导体本体（1）之间的边界部分。 由于绝缘体层（20），将构成寄生元件的导电区域分开，使得不会产生闭锁现象。 因此，可以使阱区域（2）的面积小，并且集成度可以比现有技术的LSI电路高1.4倍。

公开(公告)号：EP0097326B1

公开(公告)日：1987-01-28

申请号：EP83105880.5

申请日：1983-06-15

申请人： HITACHI, LTD.

发明人： Yamamoto, Syuichi ,  Hashimoto, Norikazu ,  Sasaki, Toshio ,  Masuhara, Toshiaki ,  Minato, Osamu ,  Tamaki, Yoichi ,  Hayashida, Tetsuya

IPC分类号： H01L21/76 ,  H01L27/08

CPC分类号： H01L21/76224 ,  H01L21/76202 ,  H01L27/0921