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公开(公告)号：EP0267628A3
公开(公告)日：1990-07-04
申请号：EP87116817.5
申请日：1987-11-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory (1) reference. In the case of mishit, the external memory (204) is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.
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公开(公告)号：EP0267628A2
公开(公告)日：1988-05-18
申请号：EP87116817.5
申请日：1987-11-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory (1) reference. In the case of mishit, the external memory (204) is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.
摘要翻译： 当顺序地执行访问，例如指令的预取或堆栈区域中的寄存器的恢复时，对连续的地址同时进行检索，并且存储结果。 当要访问连续的地址时，根据存储的结果确定命中，而不影响高速缓冲存储器（1）的引用。 在虚拟化的情况下，容易访问外部存储器（204）以缩短高速缓存存储器引用所需的开销时间。 因此，可以平均缩短访问时间。
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公开(公告)号：EP0198231A2
公开(公告)日：1986-10-22
申请号：EP86103433.8
申请日：1986-03-14
IPC分类号： G06F9/38
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor (1) for executing instructions using operand data stored in a main memory (5) comprises an instruction control unit (3) having a first associative memory (31) storing instructions read out from the main memory, and an instruction controller (300) reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory, and outputting the instruction to be executed; and an instruction execution unit (4) having a second associative memory (21) storing operand data read out from the main memory, and an instruction executioner (400) executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
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公开(公告)号：EP0267628B1
公开(公告)日：1994-07-06
申请号：EP87116817.5
申请日：1987-11-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
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公开(公告)号：EP0322769A3
公开(公告)日：1992-05-20
申请号：EP88121516.4
申请日：1988-12-22
申请人： HITACHI, LTD.
IPC分类号： G06F9/26
CPC分类号： G06F9/264
摘要： Herein disclosed is a data processing apparatus (100) such as a pipeline processing microprocessor, in which the content of a subsequent instruction to be fetched from a memory is different depending upon the formation or non-formation of a conditional branch instruction. In order to execute the conditional branch instruction, a micro-ROM contains: a first micro-instruction having an information for a conditional discrimination, an information requesting a branch ready and a subsequent micro-address of an even address; a second micro-instruction having an information requesting a branch and a subsequent micro-address of an odd address; and a third micro-instruction requesting a subsequent instruction decoding. When the branch condition is formed, the even address is outputted from a micro-address generating circuit (115). Before the branch is requested by the second micro-instruction, a micro-address analyzing circuit (130) feeds, if the brach condition is formed, the branch request signal to an instruction fetch unit (101) in response to the even address and the branch ready information of the first micro-instruction so that the time interval between the execution of the conditional branch instruction and the execution of the subsequent instruction can be shortened.
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6.发明公开
公开(公告)号：EP0318702A3
公开(公告)日：1992-04-01
申请号：EP88118026.9
申请日：1988-10-28
申请人： HITACHI, LTD.
IPC分类号： G06F9/38
CPC分类号： G06F9/3877
摘要： Data processing system has a microprocessor (1) containing a cache memory, a coprocessor (2) and a memory (3). When data is transferred from the coprocessor (2) to the memory (3), the data from the coprocessor (2) is transmitted to the cache memory in the microprocessor (1). In this constitution, when the data in the memory (3) is varied by the data from the coprocessor (2), data in the cache memory is varied thereby the matching property of the data is held.
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7.发明公开Data processor capable of simultaneous execution of two instructions 失效Datenprozessor mit derFähigkeit，zwei Befehle gleichzeitigauszuführen。
公开(公告)号：EP0471191A2
公开(公告)日：1992-02-19
申请号：EP91111770.3
申请日：1991-07-15
申请人： HITACHI, LTD.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3885
摘要： An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.
摘要翻译： 能够同时执行两个指令的数据处理器（610）的指令获取单元（640）在一个周期中从存储器（620）中取出第一和第二指令。 这样取得的第一和第二指令在被解码为第一和第二指令解码器（644,645）之前被设置在第一和第二寄存器（641,642）中。 比较器（131,132）将第一指令的目的地字段的数据与第二指令的源字段的数据进行比较。 当两个数据不一致时，并行操作控制单元（646）允许第一和第二指令下的第一和第二指令执行单元（651,652）响应于比较器的输出执行两个指令（ 131,132）。 当两个数据一致时，并行操作控制单元（646）禁止并行执行。
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公开(公告)号：EP0427245A3
公开(公告)日：1992-01-29
申请号：EP90121337.1
申请日：1990-11-07
申请人： HITACHI, LTD.
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/30167 , G06F9/3822 , G06F9/3824
摘要： First and second instructions are simultaneously fetched from a memory (620) to be respectively decoded by first and second instruction decoders (644, 645). An instruction execution unit includes a register file (650), an arithmetic and logic unit (651), and a shifter (652). A first comparator (132) compares a destination field (112) of the first instruction with a first source field (123) of the second instruction. The shifter (652) produces an output in association with immediate data (114) of the first instruction, the output being ordinarily stored in a register file (650). However, when both inputs of the comparator (132) are identical to each other, the output from the shifter (652) is supplied to an input (656) of the arithmetic and logic unit (651) via a bypass signal transmission path.
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9.发明公开Data processor with direct data transfer between coprocessor and memory 失效Datenprozessor mit direktem Datentransfer zwischen Koprozessor und Speicher。
公开(公告)号：EP0318702A2
公开(公告)日：1989-06-07
申请号：EP88118026.9
申请日：1988-10-28
申请人： HITACHI, LTD.
IPC分类号： G06F9/38
CPC分类号： G06F9/3877
摘要： Data processing system has a microprocessor (1) containing a cache memory, a coprocessor (2) and a memory (3). When data is transferred from the coprocessor (2) to the memory (3), the data from the coprocessor (2) is transmitted to the cache memory in the microprocessor (1). In this constitution, when the data in the memory (3) is varied by the data from the coprocessor (2), data in the cache memory is varied thereby the matching property of the data is held.
摘要翻译： 数据处理系统具有包含高速缓冲存储器的微处理器（1），协处理器（2）和存储器（3）。 当数据从协处理器（2）传送到存储器（3）时，来自协处理器（2）的数据被发送到微处理器（1）中的高速缓冲存储器。 在这种结构中，当存储器（3）中的数据被来自协处理器（2）的数据改变时，高速缓冲存储器中的数据被改变，从而保持数据的匹配特性。
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公开(公告)号：EP0256267A2
公开(公告)日：1988-02-24
申请号：EP87109412.4
申请日：1987-06-30
申请人： HITACHI, LTD.
IPC分类号： G06F11/14
CPC分类号： G06F11/141
摘要： A microprocessor (l00) and a peripheral equipment communicate data through a bus (l40). If an error occurs during the communication, the microprocessor starts the next bus cycle and commands retry of the data communication.
If a predetermined number of times of retry fail, or if an address signal corresponds to access to an unmounted area of the peripheral equipment or an area of an I/O equipment, the microprocessor inhibits the retry.摘要翻译： 微处理器（100）和外围设备通过总线传送数据（140）。 如果在通信期间发生错误，则微处理器启动下一个总线周期，并命令重试数据通信。 如果预定次数的重试失败，或者如果地址信号对应于对外围设备的未安装区域的访问或I / O设备的区域，则微处理器禁止重试。
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