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公开(公告)号：EP0173981A2
公开(公告)日：1986-03-12
申请号：EP85110962.9
申请日：1985-08-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A cache memory (26) is contained in a processor (1) which features a high efficiency in spite of its small capacity. In the cache memory control circuit of the invention, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory (26) and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that are to be used repeatedly, it is possible to obtain a cache memory (26) having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
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公开(公告)号：EP0173981A3
公开(公告)日：1989-05-31
申请号：EP85110962.9
申请日：1985-08-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A cache memory (26) is contained in a processor (1) which features a high efficiency in spite of its small capacity. In the cache memory control circuit of the invention, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory (26) and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that are to be used repeatedly, it is possible to obtain a cache memory (26) having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
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公开(公告)号：EP0198231A2
公开(公告)日：1986-10-22
申请号：EP86103433.8
申请日：1986-03-14
IPC分类号： G06F9/38
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor (1) for executing instructions using operand data stored in a main memory (5) comprises an instruction control unit (3) having a first associative memory (31) storing instructions read out from the main memory, and an instruction controller (300) reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory, and outputting the instruction to be executed; and an instruction execution unit (4) having a second associative memory (21) storing operand data read out from the main memory, and an instruction executioner (400) executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
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4.发明公开Semiconductor integrated circuit and method for manufacturing the same 审中-公开Integrierter Halbleiterschaltkreis und dessen Herstellungsverfahren
公开(公告)号：EP0980101A2
公开(公告)日：2000-02-16
申请号：EP99306081.3
申请日：1999-07-30
申请人： HITACHI, LTD.
发明人： Ikeda, Shuji , Yoshida, Yasuko , Kojima, Massayuki , Shiozawa, Kenji , Kimura, Mitsuyuki , Nakagawa, Norio , Ishibashi, Koichiro , Shimazaki, Yasuhisa , Osada, Kenichi , Uchiyama, Kunio
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFETs Qt和MISFET相对有意地高于SRAM外围电路和微处理器等逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。
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公开(公告)号：EP0467152A3
公开(公告)日：1993-05-05
申请号：EP91111044.3
申请日：1991-07-03
申请人： HITACHI, LTD.
CPC分类号： G06F9/3822 , G06F9/30149 , G06F9/30167 , G06F9/3867
摘要： An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder IDO, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.
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6.发明公开Single chip cache memory, and cache memory apparatus including a plurality of parallel connected single chip cache memories 失效单芯片高速缓存存储器和高速缓存存储器，包括并行连接的单芯片缓存存储器
公开(公告)号：EP0335113A3
公开(公告)日：1991-09-04
申请号：EP89103323.5
申请日：1989-02-24
申请人： HITACHI, LTD.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/601
摘要： A single chip cache memory device can operate alone, and can operate together with like cache memory devices so that the overall cache memory capacity can be expanded by the number of devices connected in parallel, with each single chip cache memory device being self-constructed so as to contain circuitry to facilitate their parallel connection. When a plurality of single chip cache memory devices are connected in parallel to constitute a large memory capacity cache memory apparatus, the access to the main memory on a cache miss-hit is permitted only for the cache memory device having a code that coincides with the code portion of the address signal, and access to the main memory for the remainder for the cache memory devices during the miss-hit is inhibited. This is accomplished by providing a specific different code to each one of the cache memory devices connected in parallel.
摘要翻译： 单芯片高速缓冲存储器设备可以单独操作，并且可以与类似的高速缓冲存储器设备一起操作，使得总体高速缓存存储器容量可以通过并联连接的设备的数量来扩展，每个单个芯片高速缓冲存储器设备是自建的 以便包含有助于其并联连接的电路。 当多个单芯片高速缓冲存储器装置并联连接以构成大的存储容量高速缓冲存储器装置时，仅对具有与该存储容量高速缓存存储器装置的代码重合的代码的高速缓存存储器件才允许对高速缓存未命中的主存储器的访问 地址信号的代码部分，以及在错过命中期间对高速缓冲存储器设备的剩余部分的访问被禁止。 这通过向并联连接的每个缓存存储器件提供特定的不同代码来实现。
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公开(公告)号：EP0198231A3
公开(公告)日：1988-10-12
申请号：EP86103433
申请日：1986-03-14
IPC分类号： G06F09/38
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor (1) for executing instructions using operand data stored in a main memory (5) comprises an instruction control unit (3) having a first associative memory (31) storing instructions read out from the main memory, and an instruction controller (300) reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory, and outputting the instruction to be executed; and an instruction execution unit (4) having a second associative memory (21) storing operand data read out from the main memory, and an instruction executioner (400) executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
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公开(公告)号：EP0591695B1
公开(公告)日：1998-02-11
申请号：EP93114493.5
申请日：1993-09-09
申请人： HITACHI, LTD.
发明人： Uchiyama, Kunio , Nishii, Osamu
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/1006 , G11C7/1072 , G11C8/12 , H04N19/423 , H04N19/61
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公开(公告)号：EP0404128B1
公开(公告)日：1997-09-03
申请号：EP90111694.7
申请日：1990-06-20
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0897
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10.发明公开Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效具有三种状态，用于当写访问产生失效信号多处理器超高速缓冲存储器系统。
公开(公告)号：EP0412353A2
公开(公告)日：1991-02-13
申请号：EP90114195.2
申请日：1990-07-24
申请人： HITACHI, LTD.
发明人： Nishii, Osamu , Uchiyama, Kunio , Aoki, Hirokazu , Oishi, Kanji , Kitano, Jun , Hatano, Susumu
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.
摘要翻译： 在本发明公开的多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器：地址总线（123），数据总线（126）上（100 2＃1和＃），以无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓冲存储器是由复录方法操作。 （：＃1 100）存在于从包括一个无效的第一状态下，一个有效的和非更新的第二状态，并有效的和更新的第三状态中选择的一个状态中的第一高速缓存的数据的状态。 第二高速缓存（100＃2）被构造像第一高速缓存中。 当第一处理器的写访问命中所述第一高速缓存中，第一高速缓存的数据的状态从所述第二状态转换到第三状态，并且第一高速缓存输出写入命中的地址和无效信号到 地址总线和无效信号线，分别。 当从第一处理器的写访问未命中的第一高速缓存中，一个块的数据是块转移从主存储器到所述第一高速缓存和无效信号的输出。 在此之后，第一高速缓存执行在传输块中的数据的写入。 在情况下，第一和第二高速缓存在第三状态与相关的地址时，处理的访问请求被馈送到地址总线（123）保持的数据，相关的高速缓存在主存储器写回恰当的数据。
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