公开(公告)号：EP0496506B1

公开(公告)日：2000-09-20

申请号：EP92300212.5

申请日：1992-01-10

申请人： Hitachi, Ltd. ,  HITACHI PROCESS COMPUTER ENGINEERING, INC.

发明人： Miyao, Takeshi ,  Araoka, Manabu ,  Nakamura, Tomoaki ,  Tanji, Masayuki ,  Kaneko, Shigenori ,  Masui, Koji ,  Iijima, Saburou ,  Yamaguchi, Shinichiro ,  Kanekawa, Nobuyasu ,  Kobayashi, Yoshiki ,  Fukumaru, Hiroaki ,  Tagiri, Katsunori

IPC分类号： G06F11/16

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

公开(公告)号：EP0496506A3

公开(公告)日：1993-07-14

申请号：EP92300212.5

申请日：1992-01-10

申请人： HITACHI, LTD. ,  HITACHI PROCESS COMPUTER ENGINEERING, INC.

发明人： Miyao, Takeshi ,  Araoka, Manabu ,  Nakamura, Tomoaki ,  Tanji, Masayuki ,  Kaneko, Shigenori ,  Masui, Koji ,  Iijima, Saburou ,  Yamaguchi, Shinichiro ,  Kanekawa, Nobuyasu ,  Kobayashi, Yoshiki ,  Fukumaru, Hiroaki ,  Tagiri, Katsunori

IPC分类号： G06F11/16

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

公开(公告)号：EP0496506A2

公开(公告)日：1992-07-29

申请号：EP92300212.5

申请日：1992-01-10

申请人： HITACHI, LTD. ,  HITACHI PROCESS COMPUTER ENGINEERING, INC.

发明人： Miyao, Takeshi ,  Araoka, Manabu ,  Nakamura, Tomoaki ,  Tanji, Masayuki ,  Kaneko, Shigenori ,  Masui, Koji ,  Iijima, Saburou ,  Yamaguchi, Shinichiro ,  Kanekawa, Nobuyasu ,  Kobayashi, Yoshiki ,  Fukumaru, Hiroaki ,  Tagiri, Katsunori

IPC分类号： G06F11/16

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

摘要翻译： 一种计算机系统，具有经由一个或多个系统总线（1-1,1-2），其连接处理单元（2-1,2-2,2-n）的复数。 每个处理单元（2-1,2-2,2-n）具有在共同的支承板的三个或更多个处理器（20-1,20-2,20-3）（PL），并通过一个公共时钟单元（控制 1000）。 这三个处理器（20-1,20-2,20-3）执行的处理器（20-1,20- 2.20〜3）相同的手术和一个故障是由三个处理器的操作的比较来检测 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）发生故障时，手术可以继续在处理单元中的另外两个处理器（20-1,20-2,20-3）（2-1,2 -2,2-N），至少临时地更换整个处理单元（2-1,2- 2.2-N）的前。 进一步，处理单元（2-1,2-2,2-n）可以具有的时钟的时钟单元（1000）内的多个（A，B）中，用一个开关装置因此做了处理器（20-1， 20〜2.20-N）正常地接收从主时钟（A）的时钟脉冲，而从接收的脉冲（一个辅助时钟B）如果主时钟（A）失败。 主，辅时钟（A，B）之间的切换涉及从时钟脉冲持续时间的比较（A，B）。 此外，高速缓冲存储器的有多个（220,221）可以共同连接到所述处理器（20-1,20-2,20-3），所以没有一个高速缓冲存储器（220,221）的失败允许处理单元（2-1 ，2-2,2-n）的继续使用其他高速缓存存储器（220,221进行操作）。 的高速缓冲存储器（220,221）中的内容的连贯性可以通过直接比较来实现，并且因此比较方法可以用于在处理器的高速缓存存储器中的数据无效，以内部（2020 1,2020-2,2020-3） （20-1,20-2,20-3），其从不同“那个”在外部高速缓冲存储器（220,221）。 协议可因此确保的相干性的确在不同的处理器单元（2-1,2-2,2-n）的的高速缓存（220,221）的数据是总是正确的。