摘要:
A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
摘要:
A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
摘要:
A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
摘要:
A safety-related communication device allowing a fail-safe signal output to be performed on the same board where the processor is disposed without the need of a special output circuit. The safety-related communication device (10) comprises a failure detection means (11) to normally output an alternating signal (21) whereas to halt an output of the alternating signal (21) at the time of malfunction; a processor (12); an output element (13) to input a signal output (22) from the processor (12) so as to generate a signal output (22'); and a power supply circuit (14) to supply power (23) to the output element (13), in which the power supply circuit (14) realizing a fail-safe signal output is incorporated in the same board where the processor (12) is disposed by arranging the power supply circuit (14) such that it converts the alternating signal (21) outputted from the failure detection means (11) so as to output the power (23) for the output element (13).
摘要:
1. A motor-driven power steering apparatus, comprises a digital converting portion (2) that receives resolver signals from a resolver; an exciting signal generator (3) that generates an exciting signal and supplies said exciting signal to the resolver; a conversion trigger generator (4) that generates a conversion trigger according to said exciting signal; an A/D converter (11) that converts said resolver signals to digital values in response to said conversion trigger; a computing portion (12) that detects a failure by computing a value of electric current in a motor (8), and supplies said current value to said motor having its shaft connected to a controlled object (9) and the resolver; and a motor control apparatus for controlling the controlled obj ect (9) including a steering column and a steering mechanism, wherein a steering force is assisted according to a steering torque detected by a torque sensor (13), the assistance to said steering force is stopped when said steering torque detected by said torque sensor exceeds a predetermined threshold value.
摘要翻译:1.一种电动机动力转向装置,包括从旋转变压器接收分解器信号的数字转换部分(2) 激励信号发生器(3),其产生激励信号并将所述激励信号提供给旋转变压器; 转换触发发生器(4),其根据所述激励信号产生转换触发; A / D转换器(11),其响应于所述转换触发而将所述分解器信号转换成数字值; 计算部分(12),通过计算电动机(8)中的电流值来检测故障,并将所述电流值提供给其轴连接到受控对象(9)和旋转变压器的所述电动机; 以及用于控制包括转向柱和转向机构的受控对象(9)的电动机控制装置,其中根据由转矩传感器(13)检测到的转向转矩来辅助转向力,对所述转向力的帮助是 当由所述转矩传感器检测到的转向转矩超过预定阈值时停止。
摘要:
A highly accurate displacement sensor using GMR elements (2) for detecting a displacement of a physical quantity such as angle is to be provided wherein a waveform distortion of output voltage is diminished. There are installed at least two Wheatstone bridge circuits having a predetermined angular offset and each comprising a plurality of GMR elements (2a-2h), the GMR elements (2a-2h) each having a fixed magnetic layer (19) set to a predetermined magnetization direction (13). An AC power supply is use as a power supply of the Wheatstone bridge circuits and a displacement of a physical quantity such as a rotational angle is detected on the basis of AC-modulated outputs from the Wheatstone bridge circuits. An anisotropic self-bias effect of a free magnetic layer (21) in each GMR element can be diminished and hence it is possible to remedy a waveform distortion of an output signal based on the anisotropic self-bias effect of the free magnetic layer (21).
摘要:
The object of the present invention is to provide a controller and a system having a highly reliable fail safe function. An ATP device which generates control data for the two systems from an ATP command speed signal, duplicates the logic unit in the ATP device so as to process each control data, provides at least two CRC data for checking the control data for each system, and changes the CRC data of the opposite logic units or selects one of the two according to the content of a failure detection signal from each of the duplicated logic units. It is realized to check the control data and the operation of each logic circuit and only when all the data, circuits, and elements operate normally, an output signal for controlling the object to be controlled is outputted and when a failure is detected in a part, an output signal is outputted. Therefore, when a failure occurs, a fail safe function for controlling on the safety side is made possible.
摘要:
A semiconductor device comprises an embedded insulation layer (101) formed on a semiconductor substrate (100), plural power semiconductor elements (2, 3) formed on a semiconductor substrate (100) on the embedded insulation layer, a trench (4) formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator (5) insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements (2, 3) such as transistors can be used, being connected to each other in series.