公开(公告)号：EP0514819B1

公开(公告)日：1996-05-01

申请号：EP92108375.4

申请日：1992-05-18

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Takata, Haruki ,  Katsumata, Kenji ,  Hirahata, Shigeru ,  Konno, Mituo ,  Ishibashi, Kouichi ,  Suzuki, Sunao

IPC分类号： H04N5/44

CPC分类号： G06T3/4007 ,  H04N7/0122

公开(公告)号：EP0514819A3

公开(公告)日：1993-03-03

申请号：EP92108375.4

申请日：1992-05-18

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Takata, Haruki ,  Katsumata, Kenji ,  Hirahata, Shigeru ,  Konno, Mituo ,  Ishibashi, Kouichi ,  Suzuki, Sunao

IPC分类号： H04N5/44

CPC分类号： G06T3/4007 ,  H04N7/0122

摘要： A wide-screen television receiver capable of converting a TV signal of a non-aspect ratio into a signal of a wide aspect ratio which can be displayed on a wide screen of the wide aspect ratio and previously visually informing the user of what part of the image of the non-aspect ratio TV signal is converted in its aspect ratio and displayed on the wide screen. The receiver includes the interpolation scan speed conversion circuit (102), the mode setting circuit (104), the aspect ratio converting circuit (103), the wide cursor adding circuit 105 and the wide display (106). The interpolation scan speed conversion circuit (102) makes a series of processes such as Y/C separation and scan line interpolation for the input video signal supplied via the input terminal (101). The aspect ratio converting circuit (103) compresses the video signal from the interpolation scan speed conversion circuit (102) in the horizontal direction by use of a memory. The magnification processing circuit (109) is provided after the aspect ratio converting circuit (103). This magnification processing circuit (109) magnifies the horizontally compressed video signal so that an arbitrary part of image specified by the mode setting circuit (104) can be magnified at given magnification powers in the horizontal and vertical directions. The wide screen display (106) displays the magnified image of the video signal without horizontal and vertical distortions on the wide screen.

公开(公告)号：EP0969658B1

公开(公告)日：2006-09-06

申请号：EP99305196.0

申请日：1999-07-01

申请人： Hitachi, Ltd. ,  Hitachi Video & Information System, Inc.

发明人： Kimura, Katsunobu ,  Matono, Takaaki ,  Takata, Haruki ,  Nagata, Tatsuo ,  Sugiyama, Masato ,  Tsuru, Yasutaka ,  Sudo, Koichi

IPC分类号： H04N5/21

CPC分类号： H04N5/21

公开(公告)号：EP0514819A2

公开(公告)日：1992-11-25

申请号：EP92108375.4

申请日：1992-05-18

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Takata, Haruki ,  Katsumata, Kenji ,  Hirahata, Shigeru ,  Konno, Mituo ,  Ishibashi, Kouichi ,  Suzuki, Sunao

IPC分类号： H04N5/44

CPC分类号： G06T3/4007 ,  H04N7/0122

摘要： A wide-screen television receiver capable of converting a TV signal of a non-aspect ratio into a signal of a wide aspect ratio which can be displayed on a wide screen of the wide aspect ratio and previously visually informing the user of what part of the image of the non-aspect ratio TV signal is converted in its aspect ratio and displayed on the wide screen. The receiver includes the interpolation scan speed conversion circuit (102), the mode setting circuit (104), the aspect ratio converting circuit (103), the wide cursor adding circuit 105 and the wide display (106). The interpolation scan speed conversion circuit (102) makes a series of processes such as Y/C separation and scan line interpolation for the input video signal supplied via the input terminal (101). The aspect ratio converting circuit (103) compresses the video signal from the interpolation scan speed conversion circuit (102) in the horizontal direction by use of a memory. The magnification processing circuit (109) is provided after the aspect ratio converting circuit (103). This magnification processing circuit (109) magnifies the horizontally compressed video signal so that an arbitrary part of image specified by the mode setting circuit (104) can be magnified at given magnification powers in the horizontal and vertical directions. The wide screen display (106) displays the magnified image of the video signal without horizontal and vertical distortions on the wide screen.

摘要翻译： 宽屏幕电视接收机能够在非宽高比的电视信号转换成宽的宽高比的一个信号，它可以在宽的宽高比的宽屏幕画面上显示与先前在视觉告知的哪一部分的所述用户的 非宽高比电视信号的图像被转换在其纵横比和显示在宽屏幕上。 该接收机包括内插扫描速度变换电路（102），所述模式设置电路（104），纵横比变换电路（103），宽光标加法电路105和宽显示（106）。 内插扫描速度变换电路（102），使一系列的处理：诸如Y / C分离和扫描线内插用于经由所述输入端（101）提供的输入视频信号。 纵横比变换电路（103），压缩从在通过使用存储器的水平方向的内插的扫描速度变换电路（102）的视频信号。 放大处理电路（109）的纵横比变换电路（103）之后提供。 这种放大处理电路（109）放大了水平方向压缩的视频信号也一样，在可以在水平和垂直方向上给定的放大率功率被放大由模式设置电路（104）中指定的图像的任意部分。 宽屏幕显示器（106）显示的视频信号的放大的图像，而不在宽屏幕上水平和垂直失真。

公开(公告)号：EP0969658A1

公开(公告)日：2000-01-05

申请号：EP99305196.0

申请日：1999-07-01

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Kimura, Katsunobu ,  Matono, Takaaki ,  Takata, Haruki ,  Nagata, Tatsuo ,  Sugiyama, Masato ,  Tsuru, Yasutaka ,  Sudo, Koichi

IPC分类号： H04N5/21

CPC分类号： H04N5/21

摘要： The present invention provides a noise reduction signal processing apparatus for reducing noise accurately. The feature of a present invention is in the following structure. That is, a noise reduction signal processing circuit is used for a display apparatus for displaying a video signal, comprising: a median filter (40) to which is inputted the video signal, and which executes a filter processing to the inputted video signal and outputs a reference signal; a subtracter (50) which is connected with the median filter (40), and which outputs a difference signal that indicates the difference between the reference signal outputted from the median filter (40) and the video signal; a minimum value detection circuit (70) which outputs the difference signal from the subtracter (50) or a limitation value, whichever is smaller, as a minimum value signal; and an adder (35) which adds a noise reduction signal on the basis of the minimum value signal output from the minimum value, detection circuit (70) and the video signal.

摘要翻译： 本发明提供了一种用于精确降低噪声的降噪信号处理装置。 本发明的特征在于以下结构。 也就是说，降噪信号处理电路用于显示视频信号的显示装置，包括：输入视频信号的中值滤波器（40），并对输入的视频信号执行滤波处理，并输出 参考信号; 减法器（50），其与中值滤波器（40）连接，并输出指示从中值滤波器（40）输出的参考信号与视频信号之间的差的差分信号; 将来自减法器（50）的差分信号或限制值（较小者）作为最小值信号输出的最小值检测电路（70） 以及加法器（35），其根据从最小值输出的最小值信号，检测电路（70）和视频信号相加噪声降低信号。

公开(公告)号：EP0947975A1

公开(公告)日：1999-10-06

申请号：EP99302559.2

申请日：1999-03-31

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Matono, Takaaki ,  Takata, Haruki ,  Kimura, Katsunobu ,  Nagata, Tatsuo ,  Sakai, Takeshi ,  Sudo, Koichi

IPC分类号： G09G3/20 ,  H04N5/202

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G2320/0276 ,  H04N5/202

摘要： In a gamma correction circuit some bits of the digital data to be converted are used to select two gamma corrected "node" voltages. The other bits are used to make a linear interpolation between the two voltages using an addition circuit.
In order to adapt the gamma correction circuit to a specific display panel, the set of "node" voltages can be programmed.

摘要翻译： 在伽马校正电路中，要被转换的数字数据的一些比特被用于选择两个经伽玛校正的“节点”电压。 其他位用于使用加法电路在两个电压之间进行线性插值。 为了使伽玛校正电路适应特定的显示面板，可以对该组“节点”电压进行编程。

公开(公告)号：EP0803855A2

公开(公告)日：1997-10-29

申请号：EP97106459.7

申请日：1997-04-18

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi ,  Urata, Hiroyuki ,  Takata, Haruki

IPC分类号： G09G3/20

CPC分类号： G06T3/4007 ,  G09G5/005 ,  G09G5/006 ,  G09G5/008 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442

摘要： A video signal processor which includes a circuit (108) for converting the number of lines in a digitized video signal, a circuit (109) for generating a display dot clock, a circuit (110) for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit (111) for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation; frck/N = fck/M = fho where M and N are natural numbers satisfying M ≠ N .

摘要翻译： 一种视频信号处理器，其包括用于，电路（109）转换的行数在一个数字化的视频信号，用于进行行号输出婷模拟像素数据生成显示点时钟的电路（110）的电路（108） 转换并具有从所述显示不同的频率做点时钟，以及用于平滑模拟像素数据的电路（111）; 和其中显示点时钟将模拟像素数据和水平同步信号SATIS外资企业等式的频率FHO的输出频率FRK的频率FCK; $其中M和N是满足M注QUAL\; N.e自然数$

公开(公告)号：EP0534220B1

公开(公告)日：1997-08-13

申请号：EP92115281.5

申请日：1992-09-07

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Takata, Haruki ,  Konno, Mitsuo ,  Ishibashi, Kouichi ,  Kaizaki, Kazuhiro ,  Matono, Takaaki ,  Haratani, Atushi

IPC分类号： H04N5/262

CPC分类号： H04N7/0122 ,  G06T3/40 ,  H04N5/2628

公开(公告)号：EP0630154A2

公开(公告)日：1994-12-21

申请号：EP94109332.0

申请日：1994-06-16

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Murata, Toshinori ,  Takata, Haruki ,  Torikoshi, Shinobu ,  Eda, Takanori ,  Ishibashi, Kouichi

IPC分类号： H04N5/44

CPC分类号： H04N7/0122 ,  H04N3/27

摘要： To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).

公开(公告)号：EP0630154A3

公开(公告)日：1995-04-12

申请号：EP94109332.0

申请日：1994-06-16

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Murata, Toshinori ,  Takata, Haruki ,  Torikoshi, Shinobu ,  Eda, Takanori ,  Ishibashi, Kouichi

IPC分类号： H04N5/44

CPC分类号： H04N7/0122 ,  H04N3/27

摘要： To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).

摘要翻译： 通过将整个图像压缩并放大到期望的大小来提供与显示单元的屏幕的纵横比匹配的图像。 响应于来自输入端子（118）的写时钟，视频信号被顺序地写入场存储器。 时钟发生电路（119）向场存储器（103）提供具有与写入时钟的频率约高4/3倍的频率的读时钟。 垂直放大控制电路（110）以与放大率对应的行周期从场存储器（103）读取视频信号，并禁止以相同周期向单行存储器（105）写入以提供行延迟输出 用于来自场存储器（13）的输出信号。 垂直内插电路（106）根据来自垂直放大控制电路（110）的控制信号，通过内插运算产生扫描线信号。