Demodulation pixel incorporating majority carrier current, buried channel and high-low junction
    2.
    发明公开
    Demodulation pixel incorporating majority carrier current, buried channel and high-low junction 审中-公开
    解调像素结合了大部分载波电流,掩埋通道和高低结点

    公开(公告)号:EP2284897A3

    公开(公告)日:2017-08-23

    申请号:EP10172890.5

    申请日:2010-08-16

    IPC分类号: H01L27/148

    CPC分类号: H01L27/14812 H01L27/14806

    摘要: A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.

    摘要翻译: 解调像素通过利用硅中电荷传输的两种效应来提高电荷传输速度和灵敏度,以实现前述优化。 第一个是基于CCD门原理的传输方法。 但是,这不限于CCD技术,而是可以在CMOS技术中实现。 在表面或甚至靠近表面的掩埋通道中的电荷传输在速度,灵敏度和低俘获噪声方面是高效的。 另外,通过激活流经衬底的多数载流子电流,在耗尽的CCD通道下面产生另一个漂移场。 该漂移场深深地位于衬底中,充当深度光生电子空穴对的高效分离器。 因此,另一大量的少数载流子被高速传送到扩散节点并被检测到。

    Method and Device for the demodulation of modulated optical signals

    公开(公告)号:EP1777811B1

    公开(公告)日:2018-10-03

    申请号:EP05405589.2

    申请日:2005-10-19

    IPC分类号: H03D7/00

    CPC分类号: H03D7/00

    摘要: A demodulation device (1) in semiconductor technology is disclosed. The device (1) is capable of demodulating an injected modulated current. The device (1) comprises an input node (IN1), a sampling stage (DG1, IG1, GS1, IG2, DG2) and at least two output nodes (D1, D2). The sampling stage DG1, IG1, GS1, IG2, DG2) comprises transfer means (GL, GM, GR) for transferring a modulated charge-current signal from the input node (IN1) to one of the output nodes (D1, D2) allocated to the respective time interval within the modulation period. The small size and the ability to reproduce the device (1) in standard semiconductor technologies make possible a cost-efficient integration of the device (1).