公开(公告)号：EP0068374B1

公开(公告)日：1987-03-25

申请号：EP82105403.8

申请日：1982-06-19

申请人： Hewlett-Packard Company

发明人： Skokan, Zdenek Emil

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  Y10S257/923

公开(公告)号：EP0068374A3

公开(公告)日：1984-05-30

申请号：EP82105403

申请日：1982-06-19

申请人： Hewlett-Packard Company

发明人： Skokan, Zdenek Emil

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  Y10S257/923

摘要： A programmable logic array (21) is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates (20) having latched complementary outputs (26A, 268). The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine.

公开(公告)号：EP0068374A2

公开(公告)日：1983-01-05

申请号：EP82105403.8

申请日：1982-06-19

申请人： Hewlett-Packard Company

发明人： Skokan, Zdenek Emil

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  Y10S257/923

摘要： A programmable logic array (21) is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates (20) having latched complementary outputs (26A, 268). The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine.