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88 条记录 (耗时 0.013 秒)

    INTEGRATED CIRCUIT BUS GRID HAVING WIRES WITH PRE-SELECTED VARIABLE WIDTHS
    1.
    发明公开
    INTEGRATED CIRCUIT BUS GRID HAVING WIRES WITH PRE-SELECTED VARIABLE WIDTHS 审中-公开
    BUSGITTER用于集成电路与选择性可变宽度LINES

    公开(公告)号：EP1442481A1

    公开(公告)日：2004-08-04

    申请号：EP02776247.5

    申请日：2002-10-17

    申请人： International Business Machines Corporation

    发明人： BUFFET, Patrick, H. ,  SUN, Yu, H.

    IPC分类号： H01L29/73 ,  H01L23/52 ,  H01L29/40 ,  H01L23/48 ,  H01L23/58

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  Y10S257/923 ,  H01L2924/00

    摘要： An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28',30') contained within two metal layer (M6',M7'). The bus grid is located within each of a plurality of contiguous rectangular regions (32'), which are defined by electrical contacts (12'). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular rgions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASICchip.

    Improved integrated multi-layer test pads and methods therefor
    4.
    发明公开
    Improved integrated multi-layer test pads and methods therefor 失效
    Verbesserte integrierte Mehrschicht-Testflächenund Methodedafür

    公开(公告)号：EP0880173A2

    公开(公告)日：1998-11-25

    申请号：EP98304060.1

    申请日：1998-05-21

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Alswede, Frank ,  Mendelson, Ron ,  Davies, William ,  Prein, Frank ,  Hoyer, Ronald

    IPC分类号： H01L21/66 ,  H01L23/485

    CPC分类号： H01L22/32 ,  Y10S257/923

    摘要： A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3 X 3 block of the first pads.

    摘要翻译： 半导体晶片上的多层测试焊盘，其包括以行和列排列的互连的第一焊盘的下层矩阵。 多层测试垫包括设置在下面的矩阵之上并且在行和列之间的氧化物层。 多层测试垫还包括布置在氧化物层上方的互连的第二焊盘的上覆矩阵。 每个第二焊盘完全重叠至少九个第一焊盘，包括围绕九个第一焊盘的中心第一焊盘的四个氧化物区域。 第一个垫中的九个排列为第一个垫的3×3个块。

    Liquid crystal device
    5.
    发明公开
    Liquid crystal device 失效
    液晶装置

    公开(公告)号：EP0806702A1

    公开(公告)日：1997-11-12

    申请号：EP97200957.5

    申请日：1989-05-16

    申请人： SEIKO EPSON CORPORATION

    发明人： Misawa, Toshiyuki ,  Oshima, Hiroyuki

    IPC分类号： G02F1/136

    CPC分类号： G02F1/13454 ,  G02F1/133345 ,  G02F1/136213 ,  G02F2001/136254 ,  G09G3/001 ,  G09G3/002 ,  G09G3/003 ,  G09G3/006 ,  G09G3/2011 ,  G09G3/3648 ,  G09G3/3659 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2330/12 ,  H01L23/4825 ,  H01L27/124 ,  H01L29/78618 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/12032 ,  H01L2924/13091 ,  Y10S257/923 ,  Y10S345/904 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A liquid crystal device for an electro-optical device is provided, the liquid crystal device including a plurality of liquid crystal cells wherein data signals are supplied to the liquid crystal cells through a plurality of field effect transistors arranged in a plurality of picture elements (292). The liquid crystal device comprises a picture element matrix (240) including a plurality of source lines and a plurality of picture elements coupled to a plurality of source lines; and a source line driving circuit coupled to the picture element matrix (240) through the plurality of the source lines, the source line driving circuit comprising a plurality of signal buses (231, 232, 233) and a plurality of sample-hold circuits (234, 235, 236) coupled to the plurality of signal buses (231, 232, 233) through a plurality of connecting lines (237, 238, 239), wherein the distance between one of the signal buses and one of the sample-hold circuits is different from the distance between another one of the signal buses and another one of the sample-hold circuits, and the resistances of the connecting line for connecting the one of the signal buses to the one of the sample-hold circuits are substantially equal to the resistance of the connecting line for connecting another one of the signal buses to another one of sample-hold circuits.

    摘要翻译： 提供一种用于电光装置的液晶装置，该液晶装置包括多个液晶单元，其中数据信号通过布置在多个像素（292）中的多个场效应晶体管提供给液晶单元 ）。 该液晶装置包括：像素矩阵（240），包括多条源极线和多个耦合到多条源极线的像素; 以及源极线驱动电路，通过所述多条源极线耦合到所述像素矩阵（240），所述源极线驱动电路包括多个信号总线（231,232,233）和多个采样保持电路（ （231,232,233）通过多条连接线（237,238,239）耦合到所述多条信号总线（231,232,233），其中所述信号总线之一与所述采样保持 电路与另一个信号总线与另一个采样保持电路之间的距离不同，并且用于将一个信号总线连接到一个采样保持电路的连接线的电阻基本相等 与用于将另一个信号总线连接到另一个采样保持电路的连接线的电阻相关联。

    Masterslice semiconductor device
    9.
    发明公开
    Masterslice semiconductor device 失效
    Masterslice半导体器件

    公开(公告)号：EP0131464A2

    公开(公告)日：1985-01-16

    申请号：EP84304669.9

    申请日：1984-07-09

    申请人： FUJITSU LIMITED

    发明人： Sato, Shinji c/o Fujitsu Limited

    IPC分类号： H01L27/02

    CPC分类号： H01L21/82 ,  H01L27/11807 ,  Y10S257/923

    摘要： A masterslice semiconductor device has two kinds of basic cells; a first kind (BC1, BC2) having a size the same as that of ordinary basic cells in a previous masterslice semiconductor device and a second kind (BCL) having a size larger than that of the first kind. A number of the large sized basic cells are arranged in columns of a semiconductor substrate to constitute a plurality of basic cells arrays (BLL) which separated in the row direction of the semiconductor substrate. Each of the basic cell arrays (BLL) comprised of basic cells of the second kind (BCL) is situated between two adjacent basic cell arrays (BL,, BL 2 ) comprised of basic cells of the first kind (BC,, BC,). Each region occupied by a basic cell arrays (BLL) of basic cells of the second kind (BCL) can be used for distributing interconnecting lines as in the previous masterslice semiconductor device. At least one basic cell of the second kind (BCL) in each such region serves to interconnect basic cells of the first kind (BC 1 , BC 2 ) in adjacent basic cell arrays (BL,, BL 2 ) and also serves to constitute an elementary circuit block, a unit cell (UC), in conjunction with basic cells of the first kind.

    摘要翻译： MASTERLICE半导体器件具有两种基本单元; 具有与先前的主半导体器件中的普通基本单元相同尺寸的第一类（BC1，BC2）和具有比第一类大的尺寸的第二类（BCL）。 多个大型基本单元排列在半导体衬底的列中以构成在半导体衬底的行方向上分离的多个基本单元阵列（BLL）。 由第二种基本单元（BCL）构成的每个基本单元阵列（BLL）位于由第一种基本单元（BC，BC，）组成的两个相邻基本单元阵列（BL，BL2）之间。 由第二种基本单元（BCL）的基本单元阵列（BLL）占据的每个区域可以用于如先前的主半片装置中那样分布互连线。 在每个这样的区域中，至少一个第二类基本单元（BCL）用于将相邻基本单元阵列（BL，BL2）中的第一类基本单元（BC1，BC2）互连，并且还用于构成基本电路块 ，一个单位细胞（UC），与第一种基本细胞结合。

    CHIP TOPOGRAPHY FOR INTEGRATED CIRCUIT COMMUNICATION CONTROLLER
    10.
    发明公开
    CHIP TOPOGRAPHY FOR INTEGRATED CIRCUIT COMMUNICATION CONTROLLER 失效
    CHIP拓扑，用于数据传输控制集成电路技术。

    公开(公告)号：EP0066605A1

    公开(公告)日：1982-12-15

    申请号：EP82900233.0

    申请日：1981-12-02

    申请人： NCR CORPORATION

    发明人： KNAPP, George William ,  SPAULDING, Bernard Browne

    IPC分类号： H01L27 ,  G06F13 ,  H01L21 ,  H04L29

    CPC分类号： G06F13/122 ,  G06F13/423 ,  H01L27/0207 ,  Y10S257/923

    摘要： Un circuit controleur integre (18) est utilise pour connecter une unite de traitement centrale (21) par l'intermediaire d'une logique d'interface de bus (20) a une pluralite de dispositifs a distance en utilisant deux canaux de communication (1, 2) pour commander leur fonctionnement. Une memoire tampon de sortie (30) recoit des donnees sous forme parallele provenant de l'unite de traitement par ce bus et un registre d'emission serielle (40) transmet ces donnees sous forme serielle aux dispositifs a distance. Un registre de reception serielle (50) recoit les donnees serielles provenant des dispositifs a distance et un tampon d'entree (54) transmet ces donnees a l'unite de traitement sous forme parallele. Des circuits de commande de synchronisation (44, 46), des logiques de commande (36), un registre de mode (70), un registre d'etat (72) et un registre de commande (75) sont inclus dans le circuit controleur pour effectuer les diverses fonctions associees a celui-ci.