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公开(公告)号：EP4344878A3
公开(公告)日：2024-06-12
申请号：EP24150979.3
申请日：2019-02-06
CPC分类号： B41J2/14072 , B41J2/14153 , B41J2/14145 , B41J2002/1440320130101 , B41J2/04543 , B41J2/0458
摘要： A die for a printhead is described herein. The die includes a number of fluid feed holes disposed in a line parallel to a longitudinal axis of the die, wherein the fluid feed holes are formed through a substrate of the die. A number of fluidic actuators are proximate to the fluid feed holes to eject fluid received from the plurality of fluid feed holes. The die includes logic circuitry to operate the fluidic actuators, wherein the logic circuitry is disposed on a first side of the plurality of fluid feed holes. Power circuitry to power the plurality of fluidic actuators is disposed on an opposite side of the fluid feed holes from the logic circuitry. Activation traces are disposed between each of the fluid feed holes to couple the logic circuitry to the power circuitry.
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公开(公告)号：EP3967498A1
公开(公告)日：2022-03-16
申请号：EP21198430.7
申请日：2019-02-06
摘要： A printhead assembly (902) includes an integrated circuit (300a,300b) to drive a plurality of fluid actuation devices. The integrated circuit (300a,300b) includes a status register (304), a plurality of interfaces including a mode interface (312), a fire interface (314), and a data interface (310) and control logic (302a,302b). The control logic (302a,302b) is to enable reading of the status register (304) in response to both a signal on the mode interface (312) transitioning to logic high with a logic high signal on the data interface (310) and transitioning a signal on the fire interface (314) to logic high with the signal on the data interface (310) floating.
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公开(公告)号：EP3954539A1
公开(公告)日：2022-02-16
申请号：EP21200726.4
申请日：2018-12-03
IPC分类号： B41J2/175 , G06K15/00 , H04L12/40 , B41J2/045 , G06F13/42 , G06F12/06 , G06F12/14 , H04L9/32
摘要： In an example, processing circuitry for use with a replaceable print apparatus component comprises a memory and first logic circuit to enable a read operation from the memory and perform processing tasks, the first logic circuit comprising a timer. The processing circuitry may be accessible via an I2C bus of a print apparatus in which the replaceable print apparatus component is installed and may be associated with a first address and at least one second address, and the first address is an I2C address for the first logic circuit. In examples, the first logic circuit is to participate in authentication of the replaceable print apparatus component by a print apparatus in which the replaceable print apparatus component is installed. The circuitry may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the processing circuit is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period as measured by the timer, ignore I2C traffic sent to the first address
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公开(公告)号：EP3904105A1
公开(公告)日：2021-11-03
申请号：EP21180999.1
申请日：2018-12-03
摘要： In an example, a logic circuitry package is configured to communicate with a print apparatus logic circuit. The logic circuit package may be configured to respond to communications sent to a first address and to at least one second address. The logic circuitry package may comprise a first logic circuit, wherein the first address is an address for the first logic circuit. The package may be configured such that, in response to a first command indicative of a task and a first time period send to the first address, the package is accessible via at least one second address for a duration of the time period.
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公开(公告)号：EP3848203A1
公开(公告)日：2021-07-14
申请号：EP21159257.1
申请日：2019-02-06
摘要： An integrated circuit to access a memory associated with a fluid ejection device includes a plurality of memory cells, an address decoder, activation logic, and configuration logic. The address decoder selects memory cells in response to an address. The activation logic activates selected memory cells based on a data signal and a fire signal. The configuration logic enables or disables access to the plurality of memory cells.
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公开(公告)号：EP3691905A1
公开(公告)日：2020-08-12
申请号：EP19823870.1
申请日：2019-12-03
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公开(公告)号：EP3688667A1
公开(公告)日：2020-08-05
申请号：EP19723908.0
申请日：2019-04-05
发明人： GARDNER, James Michael , LU, Chi , LINN, Scott A. , PANSHIN, Stephen D. , ROETHIG, David Owen , OLSEN, David N. , STUDER, Anthony D. , CUMBIE, Michael W. , WARD, Jefferson P.
IPC分类号： G06K15/00
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公开(公告)号：EP3688642A1
公开(公告)日：2020-08-05
申请号：EP19802462.2
申请日：2019-10-25
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