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    ANALOG TEST DEVICES FOR INTEGRATED CIRCUITS WITH MULTIPLE POWER DOMAINS
    1.
    发明公开
    ANALOG TEST DEVICES FOR INTEGRATED CIRCUITS WITH MULTIPLE POWER DOMAINS 审中-公开

    公开(公告)号：EP4450984A1

    公开(公告)日：2024-10-23

    申请号：EP24169497.5

    申请日：2024-04-10

    申请人： NXP B.V.

    发明人： Goyal, Prashant ,  Jain, Vigyan

    IPC分类号： G01R31/3167 ,  G01R31/3185

    摘要： An analog circuit includes an analog test bus; a plurality of analog circuits including a first analog circuit, each of the plurality of analog circuits associated with a corresponding one of a plurality of power domains; a first plurality of transmission gates coupled between the first analog circuit and the analog test bus; and a first protection device coupled between the first plurality of transmission gates and a ground reference.

    CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD
    2.
    发明公开
    CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD 审中-公开

    公开(公告)号：EP4198529A1

    公开(公告)日：2023-06-21

    申请号：EP20950892.8

    申请日：2020-08-31

    申请人： Huawei Technologies Co., Ltd.

    发明人： HUANG, Yu ,  CUI, Changming ,  HUANG, Junlin ,  FU, Haitao

    IPC分类号： G01R31/3167

    摘要： Embodiments of this application provide a test circuit (03) in a chip and a circuit test method, relate to the field of electronic technologies, and may be applied to EDA software, to resolve problems of winding congestion and complex test configuration in a current test solution. The test circuit (03) transmits input data of a test vector to a data distribution circuit (301) by using an input of a test bus (02), and transmits the input data of the test vector to a scan input channel in a circuit under test (01) by using the data distribution circuit (301). After scan of the circuit under test (01) is completed, output data of the test vector on a scan output channel in the circuit under test (01) is transmitted to an output of the test bus (02) by using the data distribution circuit (301), to complete testing of the circuit under test (01). A dynamic correspondence between the data distribution circuit (301) and the test bus (02) may be configured based on a specific test solution, so that a test resource can be dynamically allocated. In this way, the winding congestion problem can be optimized to a great extent, to reduce test costs, and a configuration process can be simplified to improve test efficiency.

    INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE
    10.
    发明授权
    INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE 有权
    体结构的自测试集成电路

    公开(公告)号：EP1820037B1

    公开(公告)日：2009-02-11

    申请号：EP05807208.3

    申请日：2005-11-23

    申请人： NXP B.V.

    发明人： PELGROM, Marcel ,  VEENDRICK, Hendricus, J., M.

    IPC分类号： G01R31/3185 ,  G01R31/3167

    CPC分类号： G01R31/318536 ,  G01R31/3167

    摘要： An integrated circuit (1) comprises a monitor (Ml, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (Ml, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SRl, SR2, SR3) and is operable to output monitor data through the shift register (SRl, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.