公开(公告)号：EP4425568A1

公开(公告)日：2024-09-04

申请号：EP21966607.0

申请日：2021-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： ZHANG, Kehao ,  LIU, Xi ,  YE, John ,  LIN, Jun

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: This application discloses a semiconductor chip, a production method therefor, and an electronic device. The semiconductor chip includes a substrate and a Fin FET located on the substrate. The Fin FET includes a fin, two sidewalls that extend across the fin and are arranged opposite to each other, and a gate structure located in a trench defined by the two sidewalls. The gate structure includes a gate dielectric layer and a gate metal layer that are stacked in sequence. The gate metal layer includes a TiSiN layer. To be specific, a TiSiN material is used to fill a gap. During filling with TiSiN, a lattice structure of TiN may be damaged due to doping of Si, so that a formed TiSiN thin film becomes an amorphous thin film, to prevent ahead-of-time sealing of a gap opening due to an excessively large grain size. Therefore, the TiSiN layer in the gate structure provided in this application has an excellent gap filling capability, and can implement seamless filling of a gap with a high depth-width ratio. In addition, TiSiN with a low silicon concentration has a resistivity similar to or even lower than that of TiN. Therefore, a low-resistivity gate structure can be implemented.

公开(公告)号：EP4443519A1

公开(公告)日：2024-10-09

申请号：EP21969287.8

申请日：2021-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： ZHANG, Kehao ,  LIU, Xi ,  YE, John ,  LIN, Jun

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/8238

Abstract: This application provides a semiconductor device, a semiconductor device manufacturing method, and an electronic device, and relates to the field of semiconductor technologies, to reduce an equivalent oxide thickness (EOT). The semiconductor device includes a transistor using a high-dielectric-constant metal gate (HKMG) structure. The high-dielectric-constant metal gate structure includes a dielectric layer, a high-dielectric-constant oxide layer, and a composite layer. The high-dielectric-constant oxide layer covers the dielectric layer. The composite layer covers the high-dielectric-constant oxide layer. The composite layer includes a first metal oxide layer, a first metal layer, and a second metal oxide layer that are sequentially disposed in a stacked manner. The first metal oxide layer and the second metal oxide layer each include a conductive metal oxide, and metal elements included in the first metal oxide layer, the first metal layer, and the second metal oxide layer are the same.

公开(公告)号：EP3300318A1

公开(公告)日：2018-03-28

申请号：EP15896752.1

申请日：2015-06-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： WANG, Dayong ,  LIU, Xi ,  LIANG, Bo

IPC: H04L12/723

CPC classification number: H04L12/465 ,  H04L45/50 ,  H04L45/586 ,  H04L45/64 ,  H04L49/354 ,  H04L49/70 ,  H04L63/0272

Abstract: Embodiments of the present invention provide a method for communicating by using a remote network element port, and an apparatus, and the method is applied to a virtual network element. The virtual network element includes a master node and an egress AP, and the master node adds a first layer VLAN tag to a virtualization packet according to a virtual port corresponding to the virtualization packet, so that the egress AP can distinguish between the virtualization packet and a non-virtualization packet according to the first layer VLAN, and the virtualization packet is correctly processed.

Abstract translation: 本发明实施例提供了一种利用远程网元端口进行通信的方法及装置，该方法应用于虚拟网元。 虚拟网元包括主节点和出口AP，主节点根据虚拟化报文对应的虚端口将第一层VLAN标签添加到虚拟化报文中，以便出口AP能够区分虚拟化报文和 根据第一层VLAN生成非虚拟化报文，并正确处理虚拟化报文。

公开(公告)号：EP4243099A1

公开(公告)日：2023-09-13

申请号：EP20963100.1

申请日：2020-11-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： QIN, Qing ,  ZHOU, Xue ,  LIU, Xi

IPC: H01L43/08 ,  H01L43/02

Abstract: Embodiments of this application provide a memory and an electronic device, and relate to the field of memory technologies, to increase a reversal speed of a free layer. The memory includes a plurality of memory cells and bit lines that are disposed in a storage region of the memory and that are distributed in an array. The memory cell includes a transistor and a magnetic tunnel junction MTJ element connected to the transistor. The MTJ element is disposed on a current transmission path between a source or a drain of the transistor and the bit line. The MTJ element includes a pinning layer, a reference layer, a tunneling layer, and a free layer that are sequentially stacked. A magnetization direction of the pinning layer is parallel to a stacking direction of layers in the MTJ. The memory further includes a first magnetic structure disposed on the current transmission path. A direction of a magnetic field generated by the first magnetic structure at the free layer is not parallel to a magnetization direction of the free layer.

公开(公告)号：EP4239636A1

公开(公告)日：2023-09-06

申请号：EP20963075.5

申请日：2020-11-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： QIN, Qing ,  ZHOU, Xue ,  LIU, Xi

IPC: G11C11/16 ,  H01L43/08

Abstract: Embodiments of this application relate to the field of memory technologies, and provide a memory and an electronic device, to resolve a problem of a large current required for flipping a free layer in an MTJ. The memory includes a plurality of storage units and bit lines distributed in an array in a storage area of the memory, where the storage unit includes a transistor and a magnetic tunnel junction MTJ element connected to the transistor. The MTJ element is disposed on a current transmission path between a source or a drain of the transistor and the bit line, the MTJ element includes a pinning layer, a reference layer, a tunneling layer, and a free layer that are stacked in sequence, and a magnetization direction of the pinning layer is parallel to a stacking direction of layers in the MTJ. The memory further includes a first magnetic structure disposed on the current transmission path and in contact with the MTJ element. An included angle between a magnetization direction of the first magnetic structure and the magnetization direction of the pinning layer is (90°, 180°].