公开(公告)号：EP3457293A1

公开(公告)日：2019-03-20

申请号：EP18174532.4

申请日：2014-04-03

申请人： Huawei Technologies Co., Ltd.

发明人： YANG, Weiguo ,  TU, Jun ,  WANG, Zuo

IPC分类号： G06F13/40 ,  H03K19/17

摘要： The application provides a field programmable gate array FPGA and a communication method. At least one application specific integrated circuit ASIC-based hard core used for communication and interconnection is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

公开(公告)号：EP3118747B1

公开(公告)日：2018-08-22

申请号：EP14887727.7

申请日：2014-04-03

申请人： Huawei Technologies Co., Ltd.

发明人： YANG, Weiguo ,  TU, Jun ,  WANG, Zuo

IPC分类号： G06F13/38 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/4022 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： The application provides a field programmable gate array FPGA and a communication method. At least one application specific integrated circuit ASIC-based hard core used for communication and interconnection is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay. A source functional module sends data to a station; the station sends the data to the high-speed exchange and interconnection unit; and the high-speed exchange and interconnection unit sends the data to a destination functional module by using a station connected to the destination functional module. In this way, data is transmitted between the source functional module and the destination functional module.

公开(公告)号：EP3118747A1

公开(公告)日：2017-01-18

申请号：EP14887727.7

申请日：2014-04-03

申请人： Huawei Technologies Co., Ltd.

发明人： YANG, Weiguo ,  TU, Jun ,  WANG, Zuo

IPC分类号： G06F13/38

CPC分类号： G06F13/4027 ,  G06F13/4022 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： The application provides a field programmable gate array FPGA and a communication method. At least one application specific integrated circuit ASIC-based hard core used for communication and interconnection is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay. A source functional module sends data to a station; the station sends the data to the high-speed exchange and interconnection unit; and the high-speed exchange and interconnection unit sends the data to a destination functional module by using a station connected to the destination functional module. In this way, data is transmitted between the source functional module and the destination functional module.

摘要翻译： 该应用提供了现场可编程门阵列FPGA和通信方法。 FPGA中嵌入至少一个专用集成电路基于ASIC的硬核，用于通信和互连。 基于ASIC的硬核包括高速交换和互连单元以及至少一个站。 每个站连接到高速交换和互连单元。 该站被配置为在FPGA中的每个功能模块和基于ASIC的硬核之间传输数据。 高速交换和互连单元被配置为在站之间传输数据。 在应用提供的FPGA中，嵌入了基于ASIC的硬核，可以促进每个功能模块与基于ASIC的硬核之间的数据交换，并减少时间延迟。 源功能模块向站发送数据; 该站将数据发送到高速交换和互连单元; 并且高速交换和互连单元通过使用连接到目的地功能模块的站将数据发送到目的地功能模块。 以这种方式，在源功能模块和目的功能模块之间传输数据。