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公开(公告)号：EP4283793A1
公开(公告)日：2023-11-29
申请号：EP22766096.6
申请日：2022-01-25
发明人： GOU, Weicheng , YE, Jinhua , WANG, Chongyang , MO, Daochun
摘要： The present disclosure provides a connector, a frame device, and a connector assembly method, and belongs to the field of communication technologies. Some terminal modules in the connector provided in the present disclosure are removed, or some terminal pairs in the terminal module are removed, so that a quantity of terminal pairs included in the connector is reduced without changing an outline dimension of the connector, thereby ensuring an original docking capability of the connector. In addition, a serial connector may be formed based on different quantities of removed terminal modules or removed terminal pairs. In this way, in the frame device, a user may select a connector of a corresponding specification based on an actual specification of a board, instead of selecting connectors of a high specification uniformly, thereby reducing a quantity of terminal pairs in an idle state in the connector, reducing waste of terminal pairs, and reducing costs of the frame device.
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2.发明公开
公开(公告)号：EP4283688A1
公开(公告)日：2023-11-29
申请号：EP22758699.7
申请日：2022-01-14
发明人： CAO, Rixiang , NONG, Zhichao , YE, Jinhua
IPC分类号： H01L31/12 , H01L31/0203 , H04B10/60
摘要： This application provides an optical receiving apparatus, an optical receiving packaging apparatus, and a related device and method. The optical receiving apparatus may include a decoupling module, a voltage regulator module, an optical-to-electrical conversion module, and an amplifier module. The decoupling module is configured to perform direct current removal processing on a first electrical signal to obtain a second electrical signal. The second electrical signal is a pulse signal. The first electrical signal and the second electrical signal carry control information for controlling a working state of the amplifier module. The voltage regulator module is configured to perform voltage regulation processing on the first electrical signal to obtain a third electrical signal with a constant amplitude. The optical-to-electrical conversion module is configured to receive a burst optical signal, and convert the received burst optical signal into a fourth electrical signal. The amplifier module is configured to amplify the fourth electrical signal under control of the control information in the second electrical signal and power supply of the third electrical signal, and output the amplified fourth electrical signal. According to this application, a requirement for a signal pin of an optical receiver in a PON system can be reduced, thereby reducing packaging costs of the optical receiver.
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公开(公告)号：EP4262331A1
公开(公告)日：2023-10-18
申请号：EP21905548.0
申请日：2021-12-03
发明人： GONG, Lili , XIE, Ertang , GAO, Feng , YE, Jinhua
摘要： This application provides a method for aligning single core boards of a multilayer circuit board. The method includes: first determining a precise region of a specified surface of a single core board, where the precise region of the specified surface of the single core board has a precise region target, and an auxiliary region of the single core board has an auxiliary target; mounting a single core board of a reference board to a board stacking machine; obtaining first coordinates of a precise region target and second coordinates of an auxiliary target of the single core board of the reference board; transporting an N th layer of single core board to the board stacking machine, where N ≥ 2; obtaining third coordinates of a precise region target and fourth coordinates of an auxiliary target of the N th layer of single core board; and stacking the N th layer of single core board and an (N-1) th layer of single core board, so that a deviation between the third coordinates and the first coordinates is not greater than a first specified threshold A, and a deviation between the fourth coordinates and the second coordinates is not greater than a second specified threshold B. Therefore, a layer deviation between single core boards is reduced, an overall layer deviation of a multilayer circuit board is reduced, and outgoing line density of the multilayer circuit board is increased.
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4.发明授权
公开(公告)号：EP1940086B1
公开(公告)日：2013-01-30
申请号：EP06775609.8
申请日：2006-09-06
发明人： DENG, Chaojun , YE, Jinhua
IPC分类号： H04J3/06
CPC分类号： H04J3/0697
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公开(公告)号：EP4395080A1
公开(公告)日：2024-07-03
申请号：EP22871912.6
申请日：2022-09-19
发明人： YE, Jinhua , WANG, Lianqiang , YE, Jilong
摘要： This application provides an orthogonal system architecture and a network device. The orthogonal system architecture includes a first circuit board, a second circuit board, a first connector, and a second connector. The first circuit board and the second circuit board are disposed vertically to each other. The first connector is electrically connected to the first circuit board via a first cable assembly, the second connector is disposed on the second circuit board and is electrically connected to the second circuit board, and the first connector is plug-connected to the second connector, to electrically connect the first circuit board to the second circuit board. When the foregoing structure is used, the first circuit board is electrically connected to the first connector via the first cable assembly. Compared with transmitting a signal through a transmission line on a board, a cable has good high-speed performance and a low signal loss. This improves system high-speed performance. In addition, a signal is transmitted through the cable, so that cross transmission lines in the first circuit board can be avoided. In this way, restrictions on a quantity of layers and a board material of the first circuit board are relaxed, and design and manufacturing difficulties of the circuit board are reduced.
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6.发明公开DATA COMMUNICATION SYSTEM, SWITCHING NETWORK BOARD AND METHOD 审中-公开VERFAHREN VERMITTLUNGSNETZWERKKARTE DATENKOMMUNIKATIONSSYSTEM
公开(公告)号：EP2104286A1
公开(公告)日：2009-09-23
申请号：EP08715232.8
申请日：2008-03-13
发明人： ZANG, Dajun , ZHOU, Da , FAN, Lingqiang , YE, Jinhua , YANG, Dongcheng , GAI, Gang , WANG, Ziqiang
IPC分类号： H04L12/56
CPC分类号： H04L49/15 , H04L49/206 , H04L49/30 , H04L49/45
摘要： A method and system of data communication, switching network board are disclosed. The data communication system includes multiple line card chassis, each including multiple line cards, at least one switching chip and at least one relay chip. The line card is respectively connected to the switching chip and the relay chip of the same line card chassis. The switching chip of one line card chassis is connected to the relay chip of at least one of other line card chassis. The relay chip of the one line card chassis is connected to the switching chip of the at least one of other line card chassis. The switching network board includes a switching chip and a relay chip. By implementing the above embodiments, the networking complexity is reduced, the networking cost is saved and the system reliability is enhanced in the case that a few line card chassis are cascaded.
摘要翻译： 公开了数据通信方法和系统，交换网板。 数据通信系统包括多个线卡机箱，每个包括多个线路卡，至少一个交换芯片和至少一个中继芯片。 线卡分别连接到同一线卡机箱的开关芯片和继电器芯片。 一个线路卡机箱的交换芯片连接到其他线路卡机箱中的至少一个的中继芯片。 一个线卡机箱的继电器芯片连接到另一个线卡机箱的至少一个的交换芯片。 交换网络板包括交换芯片和中继芯片。 通过实现上述实施例，降低了网络复杂度，节省了网络成本，并且在几个线卡机架级联的情况下提高了系统的可靠性。
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7.发明公开METHOD, ETHERNET DEVICE AND ETHERNET FOR SOLVING THE CLOCK SYNCHRONIZATION 有权VERFAHREN，以太网 - EINRICHTUNG UND ETHERNET ZURLÖSUNGDER TAKTSYNCHRISISATION
公开(公告)号：EP1940086A1
公开(公告)日：2008-07-02
申请号：EP06775609.8
申请日：2006-09-06
发明人： DENG, Chaojun , YE, Jinhua
IPC分类号： H04L12/56
CPC分类号： H04J3/0697
摘要： The present invention discloses a method and Ethernet device for clock synchronization, a method for clock synchronization in an entire Ethernet, and the relevant Ethernet. The method for clock synchronization in an Ethernet device includes: the PHY layer unit of the Ethernet device extracts a clock from the data sent by the receive unit; the MAC layer unit makes adjustments to the extracted clock according to the local clock and takes the adjusted clock as the transmit clock of the Ethernet device. The method for clock synchronization in an entire Ethernet includes: clocks of all Ethernet devices are synchronized to the clock generated by the Ethernet device at the highest level. The invention provides a method for clock synchronization so that sending and receiving of clocks in Ethernet devices can be synchronized and clock synchronization can be realized in the entire Ethernet.
摘要翻译： 本发明公开了一种用于时钟同步的方法和以太网设备，整个以太网中的时钟同步方法以及相关的以太网。 以太网设备中的时钟同步方法包括：以太网设备的PHY层单元从接收单元发送的数据提取时钟; MAC层单元根据本地时钟对提取的时钟进行调整，并将调整后的时钟作为以太网设备的发送时钟。 整个以太网时钟同步的方法包括：所有以太网设备的时钟与最高级以太网设备生成的时钟同步。 本发明提供了一种时钟同步的方法，使得以太网设备中的时钟的发送和接收可以被同步，并且可以在整个以太网中实现时钟同步。
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