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公开(公告)号：EP4053748A1
公开(公告)日：2022-09-07
申请号：EP20888862.8
申请日：2020-11-20
发明人： GAO, Bin , YAO, Peng , WANG, Kanwen , LIAO, Jianxing , WANG, Tieying , WU, Huaqiang
IPC分类号： G06N3/04
摘要： A method for data processing in a neural network system and a neural network system are provided. The method includes: inputting training data into a neural network system to obtain first output data, and adjusting, based on a deviation between the first output data and target output data, a weight value stored in at least one in-memory computing unit in some neural network arrays in a plurality of neural network arrays in the neural network system using parallel acceleration. The some neural network arrays are configured to implement computing of some neural network layers in the neural network system. The method may improve performance and recognition accuracy of the neural network system.
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公开(公告)号：EP4086816A1
公开(公告)日：2022-11-09
申请号：EP21750118.8
申请日：2021-02-05
发明人： GAO, Bin , LIU, Qi , NI, Leibin , WANG, Kanwen , WU, Huaqiang
IPC分类号： G06N3/04
摘要： This application provides a neural network circuit, including: a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit is configured to generate a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit is configured to generate a reference voltage based on a first control signal. The first control signal is determined based on first computation precision. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and is configured to output a first level signal based on the first analog voltage and the reference voltage. The first output circuit is configured to sample the first level signal based on a second control signal, and output a first computation result that meets the first computation precision, and the second control signal is used to control a frequency at which the first level signal is sampled. The sampling frequency of the first output circuit and duration of the first level signal can be adjusted to adapt to computation precision of the neural network. This avoids that a computation precision requirement cannot be met in a case of low precision, and that a waste of power consumption is caused in a case of high precision
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公开(公告)号：EP3961635A1
公开(公告)日：2022-03-02
申请号：EP20810018.0
申请日：2020-05-21
发明人： GAO, Bin , WANG, Kanwen , CHEN, Junren , ZHANG, Rui , WU, Huaqiang
IPC分类号： G11C13/00
摘要： This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1TIR. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.
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公开(公告)号：EP3605541A1
公开(公告)日：2020-02-05
申请号：EP17905627.0
申请日：2017-04-14
发明人： HU, Xing , LIANG, Chuanzeng , XIAO, Shihai , WANG, Kanwen
IPC分类号： G11C11/406
摘要： This application provides a memory refresh technology and a computer system. The memory refresh technology is applied to a computer system including a memory controller and a dynamic random access memory DRAM. According to the memory refresh technology, the memory controller receives access requests. The memory controller refreshes a first rank in the plurality of ranks at a T/N interval when a quantity of target ranks of access requests received within a first time period is less than a specified first threshold and a proportion of read requests or write requests in the access requests is greater than a specified second threshold. T is used to indicate a standard average refresh interval, and N is an integer greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.
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公开(公告)号：EP4044186A1
公开(公告)日：2022-08-17
申请号：EP20883621.3
申请日：2020-10-30
发明人： LIAO, Jianxing , WU, Wei , NI, Leibin , WANG, Kanwen , ZHANG, Rui
IPC分类号： G11C11/419
摘要： This application provides a storage and computing unit and a chip, and may be applied to a neural network system. The storage and computing unit includes: a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are connected to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be connected and disconnected; the resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor; the memristor is configured to store first data, where the resistance of the memristor is used to indicate the first data; and when a voltage used to indicate second data is input to a second electrode of the first transistor, the first transistor is configured to output a computation result of the first data and the second data from a third electrode of the first transistor. Therefore, a data computation throughput can be significantly improved, and energy consumption of a computing system can be reduced.
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公开(公告)号：EP3605542A1
公开(公告)日：2020-02-05
申请号：EP17905894.6
申请日：2017-04-14
发明人： HU, Xing , LIANG, Chuanzeng , XIAO, Shihai , WANG, Kanwen
IPC分类号： G11C11/406
摘要： This application provides a memory refresh technology and a computer system. The memory refresh technology is applied to a computer system including a memory controller and a dynamic random access memory DRAM. According to the memory refresh technology, the memory controller receives access requests. When a quantity of access requests for accessing a first rank in the DRAM that are in the received access requests is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. According to the memory refresh technology provided in this application, the first rank can be refreshed in time even if the first rank cannot be in an idle state. Therefore, impact caused on computer system performance by an increase in passive refreshes caused by refresh postponements is mitigated, memory refresh flexibility is improved, and refresh overheads are reduced.
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公开(公告)号：EP3534264A1
公开(公告)日：2019-09-04
申请号：EP16922519.0
申请日：2016-11-23
发明人： XIAO, Shihai , HU, Xing , WANG, Kanwen , YANG, Wei
IPC分类号： G06F12/02
摘要： A memory allocation method and a device are provided, where the method is applied to a computer system including a processor and a memory. The memory includes at least two rank groups, each rank group includes at least two ranks, first portions of address information in addresses of ranks in one rank group are the same, there is a mapping relationship between the first portion of address information and information about a first preset location in a physical address of a memory page, and the first preset location is a portion of page number information in the physical address. The method includes: receiving, by the processor, a memory access request carrying a to-be-accessed virtual address; when determining that no memory page has been allocated to the virtual address, selecting a target rank group from the at least two rank groups based on access traffic of the rank groups; and selecting, from idle memory pages, a to-be-allocated memory page for the memory access request, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.
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公开(公告)号：EP4283522A1
公开(公告)日：2023-11-29
申请号：EP22778378.4
申请日：2022-02-15
发明人： ZHANG, Ziyang , LIU, Tao , WANG, Kanwen , LIAO, Jianxing
IPC分类号： G06N3/04
摘要： A spiking neural network circuit and a spiking neural network-based calculation method are disclosed. The circuit includes a plurality of decompression modules and a calculation module. The plurality of decompression modules are configured to separately obtain a plurality of weight values in a compressed weight matrix and identifiers of a plurality of corresponding output neurons based on information about a plurality of input neurons. Each of the plurality of decompression modules is configured to concurrently obtain weight values with a same row number in the compressed weight matrix and identifiers of a plurality of output neurons corresponding to the weight values with the same row number. Each row of the compressed weight matrix has a same quantity of non-zero weight values. Each row of weight values corresponds to one input neuron. The calculation module is configured to separately determine corresponding membrane voltages of the plurality of output neurons based on the plurality of weight values. Calculation efficiency can be improved by using the spiking neural network circuit.
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