HYBRID INTEGRATION USING FOLDED MACH-ZEHNDER MODULATOR ARRAY BLOCK
    2.
    发明公开
    HYBRID INTEGRATION USING FOLDED MACH-ZEHNDER MODULATOR ARRAY BLOCK 审中-公开
    使用折叠式Mach-Zerder调制器阵列块的混合集成

    公开(公告)号:EP2923454A1

    公开(公告)日:2015-09-30

    申请号:EP13868232.3

    申请日:2013-12-27

    IPC分类号: H04B10/25

    摘要: An apparatus comprising a modulation block comprising a plurality of modulators, wherein each of the plurality of modulators comprises an optical input port and an optical output port, and wherein all of the optical input ports and all of the optical output ports are positioned on one face of the modulation block. Another apparatus comprising a modulation block comprising one or more Mach-Zehnder modulators (MZMs), wherein each MZM is coupled to an optical input port, an optical output port, and at least one electrical trace, wherein all of the optical input ports and all of the optical output ports are positioned on a first side of the modulation block, and wherein all of the electrical traces are positioned on a second side of the modulation block, and a planar lightwave circuit (PLC) coupled to the modulation block via an optical interface.

    摘要翻译: 公开了一种包括调制块的设备,所述调制块包括多个调制器,其中所述多个调制器中的每一个包括光学输入端口和光学输出端口,并且其中所有光学输入端口和所有光学输出端口位于 调制块的一个面。 另一装置包括包含一个或多个Mach-Zehnder调制器(MZM)的调制块,其中每个MZM耦合到光输入端口,光输出端口和至少一个电迹线,其中所有光输入端口和全部 的光输出端口定位在调制块的第一侧上,并且其中所有电迹线都位于调制块的第二侧上,以及平面光波电路(PLC),其经由光学耦合到调制块 接口。

    DISTRIBUTED MACH-ZEHNDER MODULATOR (MZM) DRIVER DELAY COMPENSATION
    4.
    发明公开
    DISTRIBUTED MACH-ZEHNDER MODULATOR (MZM) DRIVER DELAY COMPENSATION 审中-公开
    分布式MACH-ZEHNDER调制器(MZM)驱动延迟补偿

    公开(公告)号:EP3292632A1

    公开(公告)日:2018-03-14

    申请号:EP16799200.7

    申请日:2016-05-05

    IPC分类号: H03K5/00

    摘要: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.