公开(公告)号：EP2357654A4

公开(公告)日：2012-08-29

申请号：EP09823395

申请日：2009-08-04

Applicant: IBM

Inventor： MIYATAKE HISATADA

IPC: G11C15/04 ,  G06F11/10

CPC classification number: G11C15/04 ,  G06F11/1064

公开(公告)号：EP1626412A4

公开(公告)日：2006-08-30

申请号：EP04727148

申请日：2004-04-13

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  HOSOKAWA KOHJI ,  MIYATAKE HISATADA

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: It is possible to realize a DRAM of a simple circuit structure capable of effectively reducing the refresh current by setting the refresh cycle by a small step. A memory array is divided into 64 sub-arrays, each of which is further divided into eight blocks. A refresh cycle control circuit (RCCC) includes: a fuse circuit (FC0) for setting 1 or 1/2 division ratio; a divider (FD0) for dividing a pre-decode signal(ZLI0) with the division ratio which has been set; fuse circuits (FC1 to FC8) for setting 1 or 1/4 division ratio; and dividers (FD1 to FD8) for dividing pre-decode signals (ZLI1 to ZLI8) with the set division ratio. The refresh cycle control circuit (RCCC) can set the 64 or 128 ms refresh cycle for the 64 sub-arrays and the 64 or 256 ms refresh cycle for the 512 blocks.

Abstract translation: 可以通过以较小的步长设置刷新周期来实现能够有效地降低刷新电流的简单电路结构的DRAM。 存储器阵列被分成64个子阵列，每个阵列又被分成8个块。 刷新周期控制电路（RCCC）包括：用于设定1或1/2分频比的熔丝电路（FC0） 分频器（FD0），用于以已经设定的分频比对预解码信号（ZLI0）进行分频; 用于设置1或1/4分频比的熔丝电路（FC1至FC8）; 和分频器（FD1到FD8），用于以设定的分频比分割预解码信号（ZLI1到ZLI8）。 刷新周期控制电路（RCCC）可以为64个子阵列设置64或128 ms的刷新周期，并为512个块设置64或256 ms的刷新周期。

公开(公告)号：EP1463118A4

公开(公告)日：2008-07-02

申请号：EP02777998

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

CPC classification number: H01L27/224 ,  H01L21/84

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) that constitute a diode on the surface semiconductor layer of an SOI substrate. The n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.