公开(公告)号：EP1646083A1

公开(公告)日：2006-04-12

申请号：EP05447167.7

申请日：2005-07-08

申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

发明人： Van Olmen, Jan ,  Van Hove, Marleen ,  Struyf, Herbert ,  Hendrickx, Dirk ,  Vanhaelemeersch, Serge ,  Boullart, Werner

IPC分类号： H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76813

摘要： A method for patterning a dual damascene structure in a semiconductor substrate is disclosed.
The patterning is characterized as a metal hardmask based pattering eliminating at least resist poisoning and further characterized in avoiding or at least minimizing low-k damage.
Another object of the invention relates to a full-via-first patterning method.
Another object of the invention relates to a partial-via-first patterning method.

摘要翻译： 公开了一种用于在半导体衬底中图案化双镶嵌结构的方法。 图案化被表征为基于金属硬掩模的图案，至少消除了抗蚀剂中毒，并进一步表征为避免或至少使低k损伤最小化。 本发明的另一个目的涉及全通孔第一图案化方法。 本发明的另一个目的涉及部分通孔第一图案化方法。

公开(公告)号：EP1646083B1

公开(公告)日：2016-08-31

申请号：EP05447167.7

申请日：2005-07-08

申请人： IMEC

发明人： Van Olmen, Jan ,  Van Hove, Marleen ,  Struyf, Herbert ,  Hendrickx, Dirk ,  Vanhaelemeersch, Serge ,  Boullart, Werner

IPC分类号： H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76813

公开(公告)号：EP2194574A3

公开(公告)日：2012-03-21

申请号：EP09177673.2

申请日：2009-12-01

申请人： IMEC

发明人： Huyghebaert, Cedric ,  Vaes, Jan ,  Van Olmen, Jan

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76802 ,  H01L21/7684

摘要： The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),

wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.

公开(公告)号：EP2194574B1

公开(公告)日：2018-11-07

申请号：EP09177673.2

申请日：2009-12-01

申请人： IMEC VZW

发明人： Huyghebaert, Cedric ,  Vaes, Jan ,  Van Olmen, Jan

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76802 ,  H01L21/7684

摘要： The present invention is related to method for producing a semiconductor device comprising the steps of: - providing a semiconductor substrate (1), comprising active components on the surface of said substrate, - depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, - etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), - etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.

公开(公告)号：EP2194574A2

公开(公告)日：2010-06-09

申请号：EP09177673.2

申请日：2009-12-01

申请人： IMEC

发明人： Huyghebaert, Cedric ,  Vaes, Jan ,  Van Olmen, Jan

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76802 ,  H01L21/7684

摘要： The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),

wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.

摘要翻译： 本发明涉及制造半导体器件的方法，包括以下步骤： - 提供半导体衬底（1），其包括在所述衬底的表面上的有源元件， - 在表面上沉积介电材料的顶层（2） 或者至少通过所述顶层蚀刻至少一个第一开口（7），至少用第一导电材料（8）填充所述开口，并执行一个或多个第一导电材料 第一CMP步骤，以形成所述第一导电结构（3,26）， - 至少通过所述顶层蚀刻至少一个第二开口（13），至少用第二导电材料（10）填充所述开口， 以及执行第二CMP步骤以形成所述第二导电结构（4,24），其中所述方法包括在蚀刻和填充步骤之前在所述电介质顶层上沉积公共CMP停止层（5,25）的步骤 说第一个开口，所以s 辅助相同的CMP停止层用于在填充第一开口之后停止CMP处理以及在填充第二开口之后进行CMP处理。 本发明与通过本发明的方法可获得的装置相同。