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1.发明公开Semiconductor device and a method for aligining and bonding a first and second element for the fabrication of a semiconductor device 审中-公开半导体装置和方法，用于对准和两个元件的接合用于生产半导体器件
公开(公告)号：EP2075828A1
公开(公告)日：2009-07-01
申请号：EP08150775.8
申请日：2008-01-29
IPC分类号： H01L21/60 , H01L25/065
CPC分类号： H05K3/3436 , H01L21/76898 , H01L23/481 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/19043 , H05K2201/0367 , H05K2201/0394 , H05K2201/09472 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552
摘要： The present invention relates to a method for aligning and bonding elements for the fabrication of a semiconductor device, comprising providing a first element with a protrusion, the first element having a front main surface and a back main surface, providing a second element having a front main surface and a back main surface, the second element including a front portion located at the front main surface and a back portion located at the back main surface, providing at least one metal pad, forming at least one blind hole in the second element, the hole extending from the back main surface to the metal pad thereby exposing the metal pad, aligning the protrusion of the first element with the corresponding hole of the second element; inserting the protrusion of the first element into the blind hole of the second element, bonding the protrusion to the metal pad, so that the protrusion makes electrical contact with the metal pad and the first element is bonded to the second element.
摘要翻译： 本发明涉及一种用于为半导体器件的制造中对准和结合元件，包括：提供第一元件有突起，具有前具有前主表面和背面主面，提供了一个第二元件，第一元件 主表面和背面主面，所述第二元件包括位于所述前主表面和位于所述背面主面的后部的前部，提供至少一个金属垫，在所述第二元件上形成至少一个盲孔， 延伸从背面主表面到金属衬垫从而暴露金属焊盘，对准与所述第二元件的对应的孔中的第一元件的突出部的孔; 插入第一元件的突起到第二元件的盲孔时，突起接合到金属焊盘，所以没有突起与所述金属焊盘和所述第一元件电接触结合到第二元件。
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公开(公告)号：EP2047601A1
公开(公告)日：2009-04-15
申请号：EP07787041.8
申请日：2007-07-04
发明人： CRANINCKX, Jan
CPC分类号： H03M1/0682 , H03M1/1245 , H03M1/403 , H03M1/46 , H03M1/68 , H03M1/804
摘要： An analog to digital conversion circuit and method is presented. The analog to digital circuit (100) comprises a first capacitor (103), arranged for being switchably (102) connected on one side to an input voltage (101), at least one successive approximation circuit (104), a comparator (108) arranged for outputting a sign indicative of the difference between the voltage on the first capacitor (103) and a reference voltage (109), and a control block (110), arranged for converting said comparator's output into steering signals and in a digital output signal. The successive approximation circuit comprises a second capacitive structure (106), switchably connected to a pre- charge circuit (107) arranged for pre-charging the second capacitive structure (106), whereby the second capacitive structure (106) is connected in parallel with the first capacitor (103) via a charge copying circuit (105). The steering signals comprise of a signal for steering (112) said charge copying circuit (105) and for steering (113) the pre-charge circuit (107).
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公开(公告)号：EP2033327A1
公开(公告)日：2009-03-11
申请号：EP07729218.3
申请日：2007-05-16
发明人： BOUGARD, Bruno
IPC分类号： H04B1/28
CPC分类号： H04B1/406 , Y02D70/126
摘要： A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.
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公开(公告)号：EP1975791A3
公开(公告)日：2009-01-07
申请号：EP08153186.5
申请日：2008-03-21
IPC分类号： G06F9/45
CPC分类号： G06F8/52
摘要： The present invention provides a method for converting application code into optimised application code or into execution code suitable for execution on a computation engine with an architecture comprising at least a first and a second level of data memory units. The method comprises:
obtaining application code, the application code including data transfer operations between said levels of memory units; and
converting at least a part of the application code such that data transfer operations between and data layout within said memory units are modified. The modification may include an improvement with respect to energy and/or performance. The converting step comprises:
(a) scheduling of data transfer operations from a first level of memory units to a second level of memory units such that accesses of data accessed multiple times are brought closer together in time than would be the case in the original code, and thereafter,
(b) deciding on layout of the data in the second level of memory units to improve the data layout locality such that data which is accessed closer together in time is also brought closer together in the layout than would be the case in the original code,
whereby step (a) does not decide on the internal organization of at least some of the data transferred, hence fixing the scheduling of data transfer operations only partially while also partially, but not yet fully, fixing the placement of all the data transferred, thereby providing freedom to subsequent step (b).-
公开(公告)号：EP2009679A1
公开(公告)日：2008-12-31
申请号：EP07012358.3
申请日：2007-06-25
发明人： Lenoble, Damien , Collaert, Nadine
IPC分类号： H01L21/033 , H01L29/786
CPC分类号： H01L21/0337 , H01L21/26506 , H01L29/66795 , H01L29/785
摘要： The present invention provides a method for forming a semiconductor device (10) on a substrate (1) having a first major surface lying in a plane. The method comprises, after patterning the substrate (1) to form at least one structure (20) extending from the substrate (1) in a direction substantially perpendicular to the plane of the major surface of the substrate, forming locally modified regions (6) at locations in the substrate which are not covered by the at least one structure (20), thus locally increasing etching resistance of these regions (6). Forming locally modified regions may prevent under-etching of the at least one structure during further process steps in the formation of the semiconductor device (10). Forming locally modified regions (6) may be performed by implanting implantation elements into regions of the substrate (1) not covered by the at least one structure (20). The present invention furthermore provides a semiconductor device obtained by the method according to embodiments of the invention. The semiconductor devices according to embodiments of the invention have good electrical properties and good mechanical stability.
摘要翻译： 本发明提供了一种用于在具有位于平面中的第一主表面的衬底（1）上形成半导体器件（10）的方法。 该方法包括，在图案化衬底（1）以形成从衬底（1）沿基本上垂直于衬底的主表面的平面延伸的至少一个结构（20）之后，形成局部改性区域（6） 在衬底中未被至少一个结构（20）覆盖的位置处，因此局部地增加这些区域（6）的抗蚀刻性。 形成局部改性区域可以防止在形成半导体器件（10）的进一步工艺步骤期间至少一个结构的蚀刻不足。 形成局部改性区域（6）可以通过将注入元件注入未被所述至少一个结构（20）覆盖的衬底（1）的区域中来执行。 本发明还提供了通过根据本发明的实施例的方法获得的半导体器件。 根据本发明实施例的半导体器件具有良好的电性能和良好的机械稳定性。
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6.发明公开Connecting scheme for the orthogonal assembly of microstructures 有权Schaltdiagrammfürdie orthogonale Anordnung von Mikrostrukturen
公开(公告)号：EP1985579A2
公开(公告)日：2008-10-29
申请号：EP08154893.5
申请日：2008-04-21
IPC分类号： B81C3/00
CPC分类号： B81C3/008 , A61B5/04001 , A61B5/0478 , A61B2562/125 , A61N1/0529 , A61N1/0531 , B81B2201/055 , Y10T29/49222
摘要： In the present invention a device for sensing and/or actuation purposes is presented in which microstructures (20) comprising shafts (2) with different functionality and dimensions can be inserted in a modular way. That way out-of-plane connectivity, mechanical clamping between the microstructures (20) and a substrate (1) of the device, and electrical connection between electrodes (5) on the microstructures (20) and the substrate (1) can be realized. Also connections to external circuitry can be realised. Also microfluidic channels (10) in the microstructures (20) can be connected to external equipment. Also a method to fabricate and assemble the device is provided.
摘要翻译： 在本发明中，提供了用于感测和/或致动目的的装置，其中可以以模块化方式插入包括具有不同功能和尺寸的轴（2）的微结构（20）。 通过这种方式，可以实现平面外连接，微结构（20）和器件的衬底（1）之间的机械夹紧以及微结构（20）和衬底（1）上的电极（5）之间的电连接 。 还可以实现与外部电路的连接。 微结构（20）中的微流体通道（10）也可以连接到外部设备。 还提供了一种制造和组装该装置的方法。
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公开(公告)号：EP1226743B1
公开(公告)日：2008-10-01
申请号：EP00974728.8
申请日：2000-11-06
发明人： BEYNE, Eric , LECHLEITER, Francois
IPC分类号： H05K3/46
CPC分类号： H05K3/4652 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H05K3/025 , H05K3/4602 , H05K3/4655 , H05K2201/0352 , H05K2201/0358 , H05K2201/09536 , H05K2203/0152 , H05K2203/0353 , H05K2203/066 , H05K2203/068 , H05K2203/0769 , H05K2203/1581
摘要： Method and apparatus of fabricating a core laminate Printed Circuit Board structure with highly planar external surfaces is provided. A pre-formed flat material including a first resinous sub-material and a second carrier sub-material is used to planarize external surfaces. During lamination, uniform pressure is applied to the pre-formed flat sheet which covers the upper surface of the printed circuit. The resinous material of the first sub-material flows to fill the crevices, vias, etc. of the upper surface of the PCB. Moreover, due to the uniform pressure on the pre-formed flat sheet, the resinous first sub-material is planarized. This planarized surface provides a suitable base substrate for a thin film multilayer build-up structure and that provides electrical connections between the thin film top layers and the Printed Circuit Board - style core layers.
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8.发明授权Floating-body-cell memory device and a method for the manufacturing thereof 有权相同的半导体存储装置的具有浮体及其制造方法
公开(公告)号：EP1693898B1
公开(公告)日：2008-04-16
申请号：EP05447039.8
申请日：2005-02-21
IPC分类号： H01L29/786 , H01L27/12 , H01L21/336 , H01L27/108 , H01L29/78
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/10826 , H01L27/10844 , H01L27/10873 , H01L27/1203 , H01L29/42384 , H01L29/66787 , H01L29/7841 , H01L29/785
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9.发明公开Method for forming germandies and devices obtained thereof 审中-公开Verfahren zur Herstellung von Germaniden und damit hergestellte Bauelemente
公开(公告)号：EP1898452A1
公开(公告)日：2008-03-12
申请号：EP07101925.1
申请日：2007-02-07
申请人： Interuniversitair Microelektronica Centrum (IMEC) , Intel Corporation (INTEL) , Katholieke Universiteit Leuven (KUL)
发明人： Brunco, David , Opsomer, Karl , De Jaeger, Brice
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/32134 , H01L29/41783 , H01L29/45
摘要： The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process.
The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.摘要翻译： 本发明公开了一种在具有暴露的锗和暴露的电介质形貌的基底上形成锗化物的方法，从而允许锗化物形成过程的变化。 该方法包括以下步骤：在具有形貌的基底上沉积镍，执行第一热步骤以将远离地形的区域中的基本上所有沉积的镍转化成锗化物，选择性地除去未反应的镍，并进行第二热步骤以降低 形成的德国的抵抗力。
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10.发明公开Method and system for measuring contamination of a lithographical element 有权Verfahren und System zur Kontaminationsmessung bei einem lithografischen Element
公开(公告)号：EP1895365A1
公开(公告)日：2008-03-05
申请号：EP07000209.2
申请日：2007-01-05
IPC分类号： G03F7/20
CPC分类号： G01N21/94 , G01N2021/95676 , G03F7/70591 , G03F7/70916
摘要： A method and system for measuring contamination of a lithographic element, the method comprising the steps of providing a first lithographical element in a process chamber, providing a second lithographical element in said process chamber, covering part of said first lithographical element providing a reference region, providing a contaminant in the process chamber, redirecting an exposure beam via the test region of said first lithographical element towards said second lithographical element whereby at least one of said lithographical elements gets contaminated by said contaminant, measuring the level of contamination of said at least one contaminated lithographical element in said process chamber.
摘要翻译： 一种用于测量光刻元件的污染的方法和系统，所述方法包括以下步骤：在处理室中提供第一光刻元件，在所述处理室中提供第二光刻元件，覆盖提供参考区域的所述第一光刻元件的一部分， 在处理室中提供污染物，将曝光光束经由所述第一光刻元件的测试区域重定向到所述第二光刻元件，由此至少一个所述光刻元件被所述污染物污染，测量所述至少一个 污染的光刻元件在所述处理室中。
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