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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP3370252A1

    公开(公告)日：2018-09-05

    申请号：EP15907235.4

    申请日：2015-10-28

    申请人： OLYMPUS CORPORATION

    发明人： SUYAMA Takuro

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/5226 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/522

    摘要： A semiconductor apparatus 1 includes a semiconductor device 10 having a semiconductor circuit 11 formed on a first main surface 10SA, and including a via H10 having an opening at a second main surface 10SB, a first wiring 21A disposed on the first main surface 10SA of the semiconductor device 10, partially exposed at a bottom surface of the via H10, and connected to the semiconductor circuit 11, a first insulating layer 22A covering the first wiring 21A, and a redistribution wiring 30 extending from a contact portion 30A in contact with the first wiring 21A at the bottom surface of the via H10, through an inside of the via H10 and onto the second main surface 10SB, where a first through hole H21A is formed in the first wiring 21A, and the contact portion 30A is in contact with a plurality of surfaces of the first wiring 21A.

    TRANSISTOR WITH SHIELD STRUCTURE, PACKAGED DEVICE, AND METHOD OF MANUFACTURE
    4.
    发明公开
    TRANSISTOR WITH SHIELD STRUCTURE, PACKAGED DEVICE, AND METHOD OF MANUFACTURE 审中-公开
    具有屏蔽结构的晶体管，包装装置和制造方法

    公开(公告)号：EP3288074A1

    公开(公告)日：2018-02-28

    申请号：EP17157181.3

    申请日：2017-02-21

    申请人： NXP USA, Inc.

    发明人： HOLMES, Damon G. ,  BURDEAUX, David Cobb ,  CHAKRABORTY, Partha Sarathi ,  KHALIL, Ibrahim ,  RUEDA, Hernan

    IPC分类号： H01L23/482 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/3205 ,  H01L23/66 ,  H01L21/768 ,  H01L27/02 ,  H01L23/552

    CPC分类号： H01L23/552 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/4824 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L27/0203 ,  H01L2223/6644 ,  H01L2224/49175

    摘要： A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar.

    摘要翻译： 晶体管包括具有固有有源器件，第一端子和第二端子的半导体衬底。 晶体管还包括在半导体衬底的上表面上由多层介电材料和导电材料形成的互连结构。 互连结构包括柱，抽头互连和由导电材料形成的屏蔽结构。 支柱电接触第一端子，延伸穿过介电材料，并连接到第一流道。 分接头互连件电接触第二端子，延伸穿过介电材料，并且连接到第二流道。 屏蔽结构从屏蔽流道延伸穿过介电材料朝向半导体衬底。 屏蔽结构位于柱和抽头互连之间以限制抽头互连和柱之间的反馈电容。

    A SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
    5.
    发明公开
    A SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体互连结构及其制造方法

    公开(公告)号：EP3264452A1

    公开(公告)日：2018-01-03

    申请号：EP17178158.6

    申请日：2017-06-27

    申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

    发明人： LIU, Jiquan

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53238

    摘要： A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.

    摘要翻译： 介绍了半导体互连结构及其制造方法。 该制造方法包括：提供衬底结构，其中衬底结构包括：衬底; 在衬底上的第一金属层; 在所述衬底上的电介质层，其中所述电介质层覆盖所述第一金属层，并且其中所述电介质层具有延伸到所述第一金属层的孔; 以及介电层上的硬掩模层; 去除介电层上的硬掩模层; 在孔的底部选择性沉积第二金属层; 沉积第三金属层，其中第三金属层填充孔。 这种半导体互连结构提供了比常规结构更高的可靠性