公开(公告)号：EP0870224A4

公开(公告)日：1999-02-10

申请号：EP96945274

申请日：1996-12-24

申请人： INTEL CORP

发明人： DULONG CAROLE ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BUI TUAN H ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  EITAN BENNY ,  FISHER STEPHEN A ,  MAYTAL BENNY

IPC分类号： G06F7/544 ,  G06F9/302 ,  G06F7/38 ,  G06F7/52 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80

CPC分类号： G06F9/30036 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/3828

摘要： A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.

公开(公告)号：EP0847552A4

公开(公告)日：2000-01-12

申请号：EP96930495

申请日：1996-08-07

申请人： INTEL CORP

发明人： PELEG ALEXANDER D ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY ,  DULONG CAROLE ,  KOWASHI EIICHI ,  WITT WOLF ,  LIN DERRICK CHU ,  BINDAL AHMET ,  FISHER STEPHEN A ,  BUI TUAN H

IPC分类号： G06F7/53 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06F15/00 ,  G06F15/76 ,  G06F15/80

CPC分类号： G06F7/5324 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/7857 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

摘要： A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first (810), second (811), third (812), and fourth multiplier (813), wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810, 811), and second adder (851) coupled to the third and fourth multipliers (812, 813). A third storage area (871) is coupled to the adders (850, 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850, 851), respectively, as first and second data elements of a third packed data.

摘要翻译： 具有分别具有第一和第二打包数据的第一和第二存储器的处理器。 每个打包数据包括第一，第二，第三和第四数据元素。 乘加电路被耦合到第一和第二存储区域。 乘加电路包括第一（810），第二（811），第三（812）和第四乘法器（813），其中每个乘法器接收相应的一组所述数据单元。 乘加电路还包括耦合到第一和第二乘法器（810,811）的第一加法器（850），和耦合到第三和第四乘法器（812,813）的第二加法器（851）。 第三存储区（871）连接到加法器（850,851）。 第三存储区域（871）包括第一和第二字段，用于分别将第一和第二加法器（850,851）的输出保存为第三打包数据的第一和第二数据元素。