公开(公告)号：EP2589186A4

公开(公告)日：2016-11-02

申请号：EP11810139

申请日：2011-06-29

申请人： INTEL CORP

发明人： KAUSCHKE MICHAEL ,  DOSHI GAUTAM B

IPC分类号： H04L12/28 ,  G06F13/14 ,  H04L12/54 ,  H04L12/70 ,  H04L12/721 ,  H04L12/861 ,  H04L12/863 ,  H04L12/911 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935

CPC分类号： H04L47/826 ,  H04L45/06 ,  H04L47/50 ,  H04L49/00 ,  H04L49/109 ,  H04L49/1584 ,  H04L49/3063 ,  H04L49/90

摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收到的分组是否发往节点的方法，如果是，则将分组提供给I / O电路，并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。 描述和要求保护其他实施例。

公开(公告)号：EP3050048A4

公开(公告)日：2018-01-17

申请号：EP14848484

申请日：2014-10-03

申请人： INTEL CORP

发明人： ERMOLAEV IGOR ,  TOLL BRET L ,  VALENTINE ROBERT ,  SAN ADRIAN JESUS C ,  DOSHI GAUTAM B ,  CHAKRABORTY PRASENJIT ,  MALLADI RAMA K

IPC分类号： G09F9/30 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3887 ,  G06F15/8007 ,  G06F2212/454

摘要： A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.