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15 条记录 (耗时 0.009 秒)

    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION
    2.
    发明公开
    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION 失效
    当地的电力控制来降低集成电路的能耗

    公开(公告)号：EP1023656A4

    公开(公告)日：2002-07-03

    申请号：EP97944556

    申请日：1997-09-29

    申请人： INTEL CORP

    发明人： MITTAL MILLIND ,  VALENTINE ROBERT

    IPC分类号： G06F1/32

    CPC分类号： G06F9/3842 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3857

    摘要： The power consumed within an integrated circuit (IC) is reduced by throttling the performance of particular functional units (105) within the IC. The recent utilization levels of particular functional units within an IC are monitored (108), for example, by computing each functional unit's average duty cycle over its recent operating history (106). If this activity level (109) is greater than a threshold, the functional unit is operated in a reduced-power mode (110). The threshold value is set large enough to allow short bursts of high utilization to occur. An IC can dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of functional units when their utilization exceeds a sustainable level. This dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. This dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE
    3.
    发明公开
    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE 审中-公开

    公开(公告)号：EP3238026A4

    公开(公告)日：2018-08-01

    申请号：EP15873962

    申请日：2015-11-23

    申请人： INTEL CORP

    发明人： JHA ASHISH ,  VALENTINE ROBERT ,  OULD-AHMED-VALL ELMOUSTAPHA

    IPC分类号： G06F9/30 ,  G06F12/02

    CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

    摘要： An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER
    7.
    发明公开
    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER 审中-公开
    VORRICHTUNG UND VERFAHREN ZUR REVERSIERUNG UND PERMUTIERUNG VON位于EINEM MASKENREGISTER

    公开(公告)号：EP3014417A4

    公开(公告)日：2017-06-21

    申请号：EP14817656

    申请日：2014-06-17

    申请人： INTEL CORP

    发明人： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT

    IPC分类号： G06F9/06 ,  G06F9/30

    CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098

    摘要： An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

    摘要翻译： 描述了用于对掩码值执行位反转和置换的设备和方法。 例如，处理器被描述为执行指令以执行以下操作：读取存储在源掩码寄存器中的多个掩码比特，掩码比特与矢量寄存器的矢量数据元素相关联; 以及执行位反转操作以将每个屏蔽位从源屏蔽寄存器复制到目的地屏蔽寄存器，其中所述位反转操作使得来自所述源屏蔽寄存器的位在所述目的地屏蔽寄存器内反转，导致对称的镜像 原来的位排列。