公开(公告)号：EP2103100A1

公开(公告)日：2009-09-23

申请号：EP07752915.4

申请日：2007-03-12

申请人： Intel Corporation

发明人： KOSHY, Kamal ,  SUDHAKAR, Raghavan ,  MODALI, Prasad

IPC分类号： H04M7/00 ,  H04L29/02

CPC分类号： H03M13/235 ,  H03M13/2957 ,  H03M13/2987 ,  H03M13/2993 ,  H03M13/6544

摘要： Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

公开(公告)号：EP1789869B1

公开(公告)日：2010-03-17

申请号：EP05818313.8

申请日：2005-09-02

申请人： Intel Corporation

发明人： KOSHY, Kamal ,  WOLRICH, Gilbert ,  SYDIR, Jaroslaw ,  FEGHALI, Wajdi

IPC分类号： G06F7/72

CPC分类号： G06F7/728

公开(公告)号：EP1749365A1

公开(公告)日：2007-02-07

申请号：EP05736450.7

申请日：2005-04-08

申请人： Intel Corporation

发明人： KOSHY, Kamal ,  SYDIR, Jaroslaw ,  FEGHALI, Wadji

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  G09C1/00 ,  H04L2209/125 ,  H04L2209/24

摘要： An arrangement is provided for performing the KASUMI ciphering process. The arrangement includes apparatuses and methods that parallelize computations of two FI functions in KASUMI rounds within one clock cycle and computes two consecutive FL functions in the KASUMI rounds within one clock cycle.

摘要翻译： 提供了用于执行KASUMI加密过程的安排。 该装置包括在一个时钟周期内并行计算KASUMI轮次中两个FI函数的计算并且在一个时钟周期内计算KASUMI轮次中的两个连续FL函数的装置和方法。

公开(公告)号：EP1789869A2

公开(公告)日：2007-05-30

申请号：EP05818313.8

申请日：2005-09-02

申请人： INTEL CORPORATION

发明人： KOSHY, Kamal ,  WOLRICH, Gilbert ,  SYDIR, Jaroslaw ,  FEGHALI, Wajdi

IPC分类号： G06F7/72

CPC分类号： G06F7/728

摘要： An arrangement is provided for performing modular exponentiations. A modular exponentiation may be performed by using multiple Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Multiple MMEs of smaller sizes may be chained together to perform modular exponentiations of larger sizes. Additionally, a single MME of a smaller size may be scheduled to perform modular exponentiations of larger sizes. Moreover, the process of performing a Montgomery multiplication may be pipelined both horizontally and vertically. Furthermore, processes of performing two Montgomery multiplications may be interleaved and performed by the same MME or chained MMEs.

公开(公告)号：EP1747637A2

公开(公告)日：2007-01-31

申请号：EP05734068.9

申请日：2005-04-08

申请人： Intel Corporation

发明人： KOSHY, Kamal ,  SYDIR, Jaroslaw

IPC分类号： H04L9/18

CPC分类号： H04L9/065 ,  H04L2209/125

摘要： An arrangement is~ provided for performing RC4 ciphering. The arrangement includes apparatuses and methods that pipeline generation of a key stream based on a byte state array, called the S-box, which is initially generated from a secret key shared by a receiver and a transmitter in a network system. The S-box is stored in a storage device which may be a register file with two read ports and one write port. AI cache is used to store a number of bytes read from the S-box storage device.